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AM2432: SPI Transaction Delays

Part Number: AM2432
Other Parts Discussed in Thread: ADS131M08,


I am working on interfacing an ads131m08 energy meter chip to a Sitara AM2432.

I have the SPI transaction being started on a falling-edge signal interrupt from the energy meter DRDY pin.

The interrupt triggers the 40 byte SPI transaction to clock out the data frame.

I have the adc configured at SCLK = 25MHz and CLKIN = 8.192MHz

I am getting intermittent CRC fails with this configuration, but these go away when I reduce SCLK to 14MHz. I am using ~15cm jumper cables to connect the am2432 GP EVM J1 safety connector to the ads131m08 evm. Is it likely that these CRC fails are due to the limitations of using jumper cables?

Additionally, in the photo below the yellow line is SCLK and the blue line is DRDY.

Why is there a ~20uS delay before starting the SPI transaction, and why is there a delay in the middle of the SPI transaction?

  • Another related issue that I will post here:

    MCSPI_Transaction_init( &( tzSpiDrvInfo->spiTransaction ) );
    tzSpiDrvInfo->   = 0U;
    tzSpiDrvInfo->spiTransaction.dataSize  = 8;
    tzSpiDrvInfo->spiTransaction.csDisable = TRUE;
    tzSpiDrvInfo->spiTransaction.count     = ADC_DRV_ADS131M06_SPI_NUM_WORDS_FRAME * gSpiDataSizeBytes;
    tzSpiDrvInfo->spiTransaction.txBuf     = ( void * )tzSpiDrvInfo->pTxBuffer;
    tzSpiDrvInfo->spiTransaction.rxBuf     = ( void * )tzSpiDrvInfo->pRxBufferCurr;
    tzSpiDrvInfo->spiTransaction.args      = NULL;
    transferOK = MCSPI_transfer( tzSpiDrvInfo->spi_hdl, &( tzSpiDrvInfo->spiTransaction ) );

    When csDisable = TRUE, the chip select works:

    yellow is clock, blue is CS

    When csDisable = FALSE, the chip select doesnt work:

    Is this a known driver bug?

  • Hi Michael,

    I can see there are 16us delay before the SPI transfer starts and about 20us delay after the SPI transfer stops (while the CS is low). This a known bug. The SPI driver added these for compatibility. We planned to do a SPI driver overhaul to address this issue.

    I am not sure about the cause of ADC intermittent CRC errors. My guess is the jumper cables may hurt signal integrity.

    As of the csDisable, my understanding is the when it sets to FALSE, CS is forced to low. If you have large amount of data to transfer, it will reduce the delays before and after the SPI transfers.

    Best regards,