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AM2432: CLKLB

Mari Tsunoda
Expert 5726 points
Part Number: AM2432
Other Parts Discussed in Thread: SYSCONFIG

Hi Team,

My customer has a few questions about clock loopback.

  1. About CLKLB
    I searched the word "retiming purposes" from TRM, and the result told that I have to set the PADCONFIG registers of below clock signal correctly. Is that right? Is there other pins which needs CLKLB setting?
    SPI[4-0]_CLK(MCU_SPI[1-0]_CLK, OSPI0_CLK, GPMC output clock, MMC1_CLK
  2. I found the description below in TRM. that tells PADCONFIG register number for MMC1_CLK is 164.
    For MMC1_CLK signal to work properly, the RXACTIVE bit of the
    PADMMR_PADCONFIG164PADMMR_PADCONFIG164 register should be set to 0x1 because of retiming purposes.(TRM p7544)
    I couldn't find the PADCONFIG register number for SPI[4-0]_CLK and OSPI0_CLK. Could you show me the reference?
  3. Continuation from this post

    1. GPMC_CLKKB as follows:
      /* MyGPMC1 -> GPMC0_CLKLB -> GPMC0_CLKLB */
      {
      PIN_GPMC0_CLKLB, PIN_MODE(0) | \
      ((PIN_PULL_DISABLE | PIN_INPUT_ENABLE) & (~PIN_PULL_DIRECTION) & (~PIN_OUTPUT_DISABLE))
      },
      Is that true for MMC1, SPI[4-0]_CLK, OSPI0_CLK too?

      and I understand as below right?
      select MUXMODE=0
      internal pullup/down: disabled
      Input buffer : enabled
      Output buffer: enabled
      Internal pulldown is selected.
      Why is pulldown intentionally selected despite internal pullup/down is disabled? ( Is default value for PIN_PULL_DIRECTION wrong?)

Best regards,

Mari Tsunoda

  • 0
    TI__Mastermind 24613 points

    Hey Mari,

    1) The interfaces that require special consideration in regards to Clock loopback signals are:

    -MMC1 

    -GPMC0

    -OSPI0

    2)

    -MMC1_CLKLB = PADMMR_PADCONFIG164 (000F 4290h)

    -GPMC0_CLKLB = PADMMR_PADCONFIG32 (000F 4080h)

    -OSPI0_LBCLKO = PADMMR_PADCONFIG1 (000F 4004h)

    Note: Additional details regarding OSPI0_LBCLKO usage can be found in section 9.2.3.2 External Board Loopback of the AM243x datasheet.

    3a) Clock Loopback is not required for the McSPI IP (SPI[0:4]).

    3b) Internal pull down is the default value on reset. Including this setting is redundant, but will happen by default due to the nature of the SysConfig automatic code generation.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    TI__Expert 5726 points

    Hi Zack,

    Thanks for your responses.

    Regarding 3), 

    Does the same settings apply for OSPI0 and MMC1?

    edit: Also, we received a follow-up question from them:

    On the answer of 2), Section 9.2.3.2 External Board Loopback of datasheet was mentioned.
    We are going to use OSPI0 on 50MHz SCLK condition and designed PWB according to 9.2.3.1 No Loopback and Internal Pad Loopback(OSPI0_LBCLK0 pin is NC).
    How should we set PADCONFIG1 register?
    Unlike MMC1_CLKLB, GPMC0_CLKLB, OSPI0_LBCLKO has real pin, so I think that different treatment from MMC1, GPMC0 is needed for OSPI0.

    Best regards,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Expert 8090 points

    Hi Tsunoda-san,

    Addressing the follow-up question to 2):

    In OSPI0 the external loopback clock is an optional signal used in both Quad and Octal operation mode to facilitate timing closure and prevent functional failures (i.e. insufficient clock edges to sample the entire frame of data) while operating in higher transfer speeds. 

    The PADCONFIG1 register only controls the IOMUX functionality of the pin. Register OSPI_RD_DATA_CAPTURE_REG[0]BYPASS_FLD is the correct MMR/Bitfield that will determine if the loopback operation mode is enabled or not. 

    If loopback mode is disabled in the OSPI_RD_DATA_CAPTURE_REG then whether or not the pin is configured as OSPI0_LBCLKO should be irrelevant and can be left in its out of reset configuration

    Adding to 3):

    The setting provided before seem to be standard for configuring output signals and should also apply to OSPI and MMC since their loopback clocks' functionality also correspond to IOMUX 0

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Expert 5726 points

    Hi Daniel,

    Thanks for your response.

    Received another follow-up for (2) below.

    a. In TRM Table 12-3229. OSPI_RD_DATA_CAPTURE_REG Register Field Descriptions, OSPI_RD_DATA_CAPTURE_REG[0]BYPASS_FLD, it only says the following for Bypass: "Bypass the adapted loopback clock circuit."

    • So is loopback disabled mean set to 0 or 1?
    • How can they enable loopback?
      • If enabled, what settings do they need to change?
    • Is this register the only setting to enable loopback mode?

    b. How should they configure PADCONFIG1 register for conditions below?

    • QSPI flash at 50MHz clock
    • N20 pin (OSPI0_LBCLKO) not connected

    They are planning on configuring the register as below but is this correct?

    • [31]LOCK=0(default)
    • [21]TX_DIS=0(Driver is enabled)
    • [20:19]DRV_STR=0(default)
    • [18]RXACTIVE=1(receiver enabled)
    • [17]PULLTYPESEL=0(default)
    • [16]PULLUDEN=1(disabled)
    • [14]ST_EN=1(default)
    • [13:11]DEBOUNCE_SEL=0(default)
    • [3:0]MUXMODE=0(OSPI_LBCLKO)

    c. In the same conditions above (in b), when configuring BOOTMODE[6:3]=0010(QSPI), what should BOOTMODE[8](Iclk) be set to? (Iclock source external or internal?)

    Best regards,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Expert 5726 points

    Hi Daniel,

    Any update on this? If I need to post a new thread, please let me know.

    Best regards,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Expert 5726 points

    Hi Daniel, Zack,

    We have an in-person meeting with the customer this week so could I receive a response soon?

    Best regards,

    Mari

  • 0 in reply to Mari Tsunoda
    TI__Expert 8090 points

    Hi Tsunoda-san,

    a) Yes, loopback mode is enabled by configuring that register. Refer to section 12.3.2.4.2.1 Read Data Capture in the TRM, it describes the following:

    "The loopback mode is enabled by writing 0x0 to OSPI_RD_DATA_CAPTURE_REG[0] BYPASS_FLD. The taps
    are selected by programming OSPI_RD_DATA_CAPTURE_REG[4-1] DELAY_FLD field. The taps delay the read
    data capturing logic by the programmed number of OSPI_RCLK cycles."

    Loopback mode is disabled by default with a value of 1h out of reset. To enable it you will have to write 0h to OSPI_RD_DATA_CAPTURE_REG[0]BYPASS_FLD. This is the only register that controls the enabling of the loopback clock in OSPI. The functional operation of the loopback clock depends on different settings that you can refer to in sections:

    12.3.2.4.2.1 Read Data Capture (already mentioned above) and 

    12.3.2.4.16.2 Read Data Capturing by the PHY Module

    We'll look into b) and c) and get back to you with the second half of this thread, no need for another post right now.

    Best

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Mastermind 24613 points

    Hi Tsunoda-san,

    b) Minor changes below regarding unused OSPI_CLKLB configuration:

    • [31]LOCK=0(default)
    • [21]TX_DIS=1(Driver is disabled)
    • [20:19]DRV_STR=0(default)
    • [18]RXACTIVE=0(receiver disabled)
    • [17]PULLTYPESEL=0(default)
    • [16]PULLUDEN=1(disabled)
    • [14]ST_EN=1(default)
    • [13:11]DEBOUNCE_SEL=0(default)
    • [3:0]MUXMODE=0(OSPI_LBCLKO)

    Disabling the transmit and receive buffers decreases the chance that spurious signals are interpreted on the pin that may result in undefined behavior.

    c) The content below was extracted from the Initialization chapter of the AM64x/AM243x device TRM (https://www.ti.com/lit/pdf/spruim2)

    When booting from any of the SPI boot modes, BOOTMODE pin settings will depend on operation during
    normal operation
    – To support high speed OSPI with the DQS signal during normal operation, set BOOTMODE8=1 to use
    internal iclk during boot and ensure signal LBCLKO is a no connect (ie, absolutely no trace can be
    connected to LBCLKO). The ROM boot will operate OSPI at low speed (50MHz), and during normal
    operation, the OSPI interface can use the DQS signal to operate the interface at high speeds.
    – To support high speed OSPI or QSPI without DQS signal (ie, using the LBCLKO signal to support
    loopback clock), then set BOOTMODE8=0 to use external clock during boot. In this case, ROM boot and
    normal operation will use the externally looped back clock signal LBCLKO. Board designers should refer
    to the device specific datasheet to undertstand board routing guidelines for the LBCLKO signal.
    – To support only low speed OSPI\xSPI\QSPI\SPI operation (ie, <=50MHz OSPI clock), set
    BOOTMODE8=1 to use internal iclk, and ensure signal LBCLKO is a no connect (ie, absolutely no trace
    can be connected to LBCLKO). Operation for both ROM boot and normal operating mode will clock the
    interface at low speed and use the internally pad looped back clock. The DQS and LBCLKO signals will
    not be used during boot or normal operation

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    TI__Expert 5726 points

    Hi Zack, Daniel,

    Thanks for your responses. I will let you know if they have any follow-up questions.

    Best,

    Mari

  • 0 in reply to Fleenor
    TI__Expert 5726 points

    Hi Zack, Daniel,

    I received some follow-up questions from the customer.

    I'd like to confirm my understanding of LBCLKO before I respond to the customer:

    • If internal iclk is selected via BOOTMODE[8] = 1, then LBCLKO should be NC
    • If external iclk is selected via BOOTMODE[8] = 0, then LBCLKO or DQS can be selected via CTRLMMR_OSPI0_CLKSEL[4]LOOPCLK_SEL.

    Is my understanding above correct?

    They are still confused by what the "loopback" points to in the OSPI_RD_DATA_CAPTURE_REG[0]BYPASS_FLD (TRM pg.7309). 

    • Does this correspond to whether internal or external iclk is selected?

    For example, in my customer's situation below:

    Mari Tsunoda said:
    • QSPI flash at 50MHz clock
    • N20 pin (OSPI0_LBCLKO) not connected

    Is the correct setting OSPI_RD_DATA_CAPTURE_REG[0]BYPASS_FLD = 1 because internal iclk is selected?

     

    Regarding the PADCONFIG1 settings, in a previous E2E thread, you mentioned that the internal pull should be enabled depending on the functionality. Does this apply here? 

    The errata below also indicates that internal pull should be enabled. Therefore, should internal pull be enabled? ( [16]PULLUDEN=0(enabled) )

    Best regards,

    Mari Tsunoda

  • 0 in reply to Mari Tsunoda
    TI__Expert 8090 points

    Hi Tsunoda-san,

    Mari Tsunoda said:

    I'd like to confirm my understanding of LBCLKO before I respond to the customer:

    • If internal iclk is selected via BOOTMODE[8] = 1, then LBCLKO should be NC
    • If external iclk is selected via BOOTMODE[8] = 0, then LBCLKO or DQS can be selected via CTRLMMR_OSPI0_CLKSEL[4]LOOPCLK_SEL.

    Yes this is correct, this is also stated in the TRM Section 4.4.1 OSPI\xSPI\QSPI\SPI Boot:

    Mari Tsunoda said:

    They are still confused by what the "loopback" points to in the OSPI_RD_DATA_CAPTURE_REG[0]BYPASS_FLD (TRM pg.7309). 

    • Does this correspond to whether internal or external iclk is selected?

    No, this register bitfield only controls whether or not loopback is enabled or not. Setting this to 0 will tell the device to not bypass the loopback clock circuit but not if internal or external iclk is selected, this is done by the value of BOOTMODE8:

     

    I will reach out to the team for comments on the PADCONFIG1 settings question

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Mastermind 24613 points

    Hi Tsunoda-san,

    Regarding the PADCONFIG1 settings, in a previous E2E thread, you mentioned that the internal pull should be enabled depending on the functionality. Does this apply here? 

    Yes, it does apply.

    The errata below also indicates that internal pull should be enabled. Therefore, should internal pull be enabled? ( [16]PULLUDEN=0(enabled) )

     Yes, internal pull should be enabled.

    Best Regards,

    Zackary Fleenor