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TMS570LS1224: Enabling FIQ causes prefetch abort after a power on reset

Mahendran Lakshmipathy
Prodigy 20 points
Part Number: TMS570LS1224

Hi,


I am facing a scenario where enabling FIQ causes a prefetch abort only during a power on reset.

I am disconnecting the target after flashing the software and then i am doing a power on reset,  the system didnt run as expected to debug the issue i connected back to the target and found that the system is stuck in prefetch handler.

Instruction fault status register = 0x00000008
Instruction fault Address register = 0x3E5BB2B0



The SPSR_ABT indicates that the system was in FIQ mode. Only ESM interrupts are FIQ and all other interrupts are configured as IRQ

The system is running as expected in debug mode but not after a power on reset and I am not facing this problem if FIQ isnt enabled

As  a work around to this problem I am doing a S/W reset in prefetch abort handler and after the S/W reset the system runs as expected, but I really dont understand the root cause behind this. It would be really great if i could some help in resolving this issue.

Thanks.

  • 0
    TI__Guru**** 193196 points
    Mahendran Lakshmipathy said:
    found that the system is stuck in prefetch handler.

    Possible reason for prefetch abort may be:

    • ECC Error on the instruction read: The IFAR register provides the address that caused the error to be detected. The auxiliary IFSR indicates source of the ECC error.

    • Wrong return address or branch address - Return address being corrupted - Branch address is corrupted

    The ECC values for all of the Flash memory space must be programmed into the Flash before the program/data can be read. This can be done by generating the correct values of the ECC with Linker CMD file. The Cortex R5F CPU may generate speculative fetches to any location within the Flash memory space. A speculative fetch to a location with invalid ECC may create an abort.

    Mahendran Lakshmipathy said:
    The system is running as expected in debug mode but not after a power on reset and I am not facing this problem if FIQ isnt enabled

    What is the value of ESM status register 2 and ESM Status Shadow Register 2? If FIQ is enabled, any error in ESM group 2 will trigger ESM HIGH interrupt (FIQ)? 

  • 0 in reply to QJ Wang
    Prodigy 20 points

    Hi Wang,

    Thanks for your reply.

    I did as per your suggestion ( ECC generation using linker file) but unfortunately that didn't resolve my issue, the behavior is same for linker generated ECC and CCS generated ECC.

    Auxiliary IFSR value is 0x00

    I am attaching the snapshot of CP15 register set



    Linker file

        /* These configuration settings are required for all SafeRTOS based
         * applications.
         * If the whole build is using ARM mode then VECTORS length can be 0x20.
         * When using thumb mode, 0x60 is required to accommodate the interwork
         * code. */

        VECTORS     (X)      : origin=0x00000000 length=0x00000060 vfill=0xFFFFFFFF
        KERN_FUNC   (RX)     : origin=0x00000060 length=0x0000FFA0 vfill=0xFFFFFFFF
        FLASH_API   (RX)     : origin=0x00010000 length=0x00010000 vfill=0xFFFFFFFF
        FLASH0      (RX)     : origin=0x00020000 length=0x0011fc00 vfill=0xFFFFFFFF
        EPK         (RX)     : origin=0x0013fc00 length=0x200 vfill=0xFFFFFFFF
        FLASH1      (RX)     : origin=0x0013fe00 length=0x100 vfill=0xFFFFFFFF
        CRC_TABLE   (RX)     : origin=0x0013FF00 length=0x00000100 vfill=0xFFFFFFFF


        ECC_VEC           : origin=(0xF0400000 + (start(VECTORS) >> 3)) length=(size(VECTORS) >> 3)
                               ECC={ algorithm=algoR4F021, input_range=VECTORS }
        ECC_KERN_FLASH    : origin=(0xF0400000 + (start(KERN_FUNC) >> 3)) length=(size(KERN_FUNC) >> 3)
                               ECC={ algorithm=algoR4F021, input_range=KERN_FUNC }
        ECC_FLASH_API     : origin=(0xF0400000 + (start(FLASH_API) >> 3)) length=(size(FLASH_API) >> 3)
                               ECC={ algorithm=algoR4F021, input_range=FLASH_API }
        ECC_FLASH0        : origin=(0xF0400000 + (start(FLASH0) >> 3)) length=(size(FLASH0) >> 3)
                               ECC={ algorithm=algoR4F021, input_range=FLASH0 }
        ECC_EPK           : origin=(0xF0400000 + (start(EPK) >> 3)) length=(size(EPK) >> 3)
                               ECC={ algorithm=algoR4F021, input_range=EPK }
        ECC_FLASH1        : origin=(0xF0400000 + (start(FLASH1) >> 3)) length=(size(FLASH1) >> 3)
                               ECC={ algorithm=algoR4F021, input_range=FLASH1 }
        ECC_CRC_TABLE     : origin=(0xF0400000 + (start(CRC_TABLE) >> 3)) length=(size(CRC_TABLE) >> 3)
                               ECC={ algorithm=algoR4F021, input_range=CRC_TABLE }

    ECC
    {
        algoR4F021 : address_mask = 0x003ffff8 /* Address Bits 21:3 */
        hamming_mask = R4         /* Use R4 build in Mask */
        parity_mask  = 0x0c       /* Set which ECC bits are Even and Odd parity */
        mirroring    = F021       /* RM4x and TMS570LSx are build in F021 */
    }



    QJ : What is the value of ESM status register 2 and ESM Status Shadow Register 2? If FIQ is enabled, any error in ESM group 2 will trigger ESM HIGH interrupt (FIQ)?  -  No fault is set by ESM when system is running in debug mode.

    If this fault is related to Flash ECC then a software reset on prefetch handler shouldn't be masking this issue right ?

  • 0 in reply to Mahendran Lakshmipathy
    TI__Guru**** 193196 points

    To enable the ECC generation through Linker CMD file, the linker option should be enabled,

    and uncheck the "Auto ECC Generation"

  • 0 in reply to QJ Wang
    Prodigy 20 points

    Hi Wang,

    Thanks for your reply!

    Yes I did enable those options. 

    Initially i was calling checkRAMUERRTest() right before running ECC test on SRAM



    I am not facing prefetch issue on POR if I run the test after __TI_auto_init() function and not before CheckRAMECC




    Are there any preconditions for running SRAM address decode test ? Why the issue is seen if the test is ran before CheckRAMECC ? 

  • 0 in reply to Mahendran Lakshmipathy
    TI__Guru**** 193196 points
    Mahendran Lakshmipathy said:
    Are there any preconditions for running SRAM address decode test ?

    No. There is no precondition for running this test.

    Mahendran Lakshmipathy said:
    Why the issue is seen if the test is ran before CheckRAMECC ? 

    The checkRAMUERRTest() is to test the redundant address decode and compare logic. The checkRAMECC() is to test the CPU ECC mechanism for RAM accesses. It should be fine to run checkRAMUERRTest() before or after checkRAMECC() test.

    I am not sure why you got prefetch exception when running checkRAMUERRTest() before checkRAMECC(). 

    Please disable the interrupt before running those selftest.