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TM4C123GH6PM: ADC0 works but ADC1 not

Kevin Hinrichs
Prodigy 180 points

Part Number: TM4C123GH6PM

ADC0 works but ADC1 not. I have to change the udma channel from 14 to 24 because i need the channel 14 for diffrent thing.

So i have to use now the adc1 and not the adc0.

When i use the Code with ADC1 the dma Interupt comes immediately after start the dma channels.

And the dma dont transfer the items. And i get a lot of overflows.

My Code:

void ADC0Seq0IntHandler(void)
{
    ADCIntClear(ADC0_BASE, 0);
    
    DEBUG_PA2 = GPIO_PIN_2; // ADC Int
    
    if ((uDMAChannelModeGet(UDMA_CH14_ADC0_0 | UDMA_PRI_SELECT) == 
         UDMA_MODE_STOP) && 
        (uDMAChannelModeGet(UDMA_CH14_ADC0_0 | UDMA_ALT_SELECT) == 
         UDMA_MODE_STOP))
        {
            DEBUG_PC4 = 0; // Rec
            
            MAP_uDMAChannelDisable(UDMA_CH14_ADC0_0);
            MAP_ADCSequenceDisable(ADC0_BASE, 0);
            MAP_ADCIntClear(ADC0_BASE, 0);
            MAP_ADCSequenceDMADisable(ADC0_BASE, 0);
            MAP_ADCIntDisable(ADC0_BASE, 0);
            MAP_IntDisable(INT_ADC0SS0);
            ADCSequenceOverflowClear(ADC0_BASE, 0);
            ADCSequenceUnderflowClear(ADC0_BASE, 0);
        }
    
    overflow = ADCSequenceOverflow(ADC0_BASE, 0);
    underflow = ADCSequenceUnderflow(ADC0_BASE, 0);
    
    
    if (overflow)
    {
        ADCSequenceOverflowClear(ADC0_BASE, 0);
        overflowCounter++;
    }
    
    if (underflow)
    {
        ADCSequenceUnderflowClear(ADC0_BASE, 0);
        underflowCounter++;
    }
    
    DEBUG_PA2 = 0; // ADC Int
}

void ADC1Seq0IntHandler(void)
{
    ADCIntClear(ADC1_BASE, 0);
    
    DEBUG_PA2 = GPIO_PIN_2; // ADC Int
    
    if ((uDMAChannelModeGet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT) == 
         UDMA_MODE_STOP) && 
        (uDMAChannelModeGet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT) == 
         UDMA_MODE_STOP))
        {
            DEBUG_PC4 = 0; // Rec
            
            MAP_uDMAChannelDisable(UDMA_CH24_ADC1_0);
            MAP_ADCSequenceDisable(ADC1_BASE, 0);
            MAP_ADCIntClear(ADC1_BASE, 0);
            MAP_ADCSequenceDMADisable(ADC1_BASE, 0);
            MAP_ADCIntDisable(ADC1_BASE, 0);
            MAP_IntDisable(INT_ADC1SS0);
            ADCSequenceOverflowClear(ADC1_BASE, 0);
            ADCSequenceUnderflowClear(ADC1_BASE, 0);
        }
    
    overflow = ADCSequenceOverflow(ADC1_BASE, 0);
    underflow = ADCSequenceUnderflow(ADC1_BASE, 0);
    
    
    if (overflow)
    {
        ADCSequenceOverflowClear(ADC1_BASE, 0);
        overflowCounter++;
    }
    
    if (underflow)
    {
        ADCSequenceUnderflowClear(ADC1_BASE, 0);
        underflowCounter++;
    }
    
    DEBUG_PA2 = 0; // ADC Int
}

void init_uDMA_MIC0()
{
    // adc mic setup
    MAP_uDMAChannelAttributeDisable(UDMA_CH14_ADC0_0,
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK);
    
    MAP_uDMAChannelControlSet(UDMA_CH14_ADC0_0 | UDMA_PRI_SELECT,
                              UDMA_SIZE_16 | UDMA_SRC_INC_NONE | 
                              UDMA_DST_INC_16 | UDMA_ARB_4);
    
    MAP_uDMAChannelControlSet(UDMA_CH14_ADC0_0 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_16 | UDMA_SRC_INC_NONE | 
                              UDMA_DST_INC_16 | UDMA_ARB_4);
    
    MAP_uDMAChannelAttributeEnable(UDMA_CH14_ADC0_0, UDMA_ATTR_USEBURST);
}

void init_uDMA_MIC1()
{
    // adc mic setup
    MAP_uDMAChannelAttributeDisable(UDMA_CH24_ADC1_0,
                                    UDMA_ATTR_ALTSELECT | 
                                    UDMA_ATTR_HIGH_PRIORITY | 
                                    UDMA_ATTR_REQMASK);
    
    MAP_uDMAChannelControlSet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT,
                              UDMA_SIZE_16 | UDMA_SRC_INC_NONE | 
                              UDMA_DST_INC_16 | UDMA_ARB_4);
    
    MAP_uDMAChannelControlSet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT, 
                              UDMA_SIZE_16 | UDMA_SRC_INC_NONE | 
                              UDMA_DST_INC_16 | UDMA_ARB_4);
    
    MAP_uDMAChannelAttributeEnable(UDMA_CH24_ADC1_0, UDMA_ATTR_USEBURST);
}

void init_ADC0()
{
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0));
    
    // adc mic setup
    MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2);
    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | 
                      ADC_CLOCK_RATE_FULL, 1);
    
    SysCtlDelay(10);
    
    MAP_IntDisable(INT_ADC0SS0);
    MAP_ADCIntDisable(ADC0_BASE, 0);
    MAP_ADCSequenceDisable(ADC0_BASE, 0);
    MAP_ADCHardwareOversampleConfigure(ADC0_BASE, ADC_HARDWARE_OVERSAMPLE);
    MAP_ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_ALWAYS, 0);
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 3, ADC_CTL_CH5 | ADC_CTL_IE);
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 4, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 5, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 6, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 7, ADC_CTL_CH5 | ADC_CTL_IE);
}

void init_ADC1()
{
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC0);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC0));
    
    MAP_SysCtlPeripheralEnable(SYSCTL_PERIPH_ADC1);
    while(!MAP_SysCtlPeripheralReady(SYSCTL_PERIPH_ADC1));
    
    // adc mic setup
    MAP_GPIOPinTypeADC(GPIO_PORTD_BASE, GPIO_PIN_2);
    ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PIOSC | 
                      ADC_CLOCK_RATE_FULL, 1);
    
    SysCtlDelay(10);
    
    MAP_IntDisable(INT_ADC1SS0);
    MAP_ADCIntDisable(ADC1_BASE, 0);
    MAP_ADCSequenceDisable(ADC1_BASE, 0);
    MAP_ADCHardwareOversampleConfigure(ADC1_BASE, ADC_HARDWARE_OVERSAMPLE);
    MAP_ADCSequenceConfigure(ADC1_BASE, 0, ADC_TRIGGER_ALWAYS, 0);
    MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 0, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 1, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 2, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 3, ADC_CTL_CH5 | ADC_CTL_IE);
    MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 4, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 5, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 6, ADC_CTL_CH5);
    MAP_ADCSequenceStepConfigure(ADC1_BASE, 0, 7, ADC_CTL_CH5 | ADC_CTL_IE);
}

//
        // ADC0
        //
        MAP_uDMAChannelTransferSet(UDMA_CH14_ADC0_0 | UDMA_PRI_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *)(ADC0_BASE + ADC_O_SSFIFO0),
                           &ADCBufferForFft, FFT_SIZE);
        
        MAP_uDMAChannelTransferSet(UDMA_CH14_ADC0_0 | UDMA_ALT_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *)(ADC0_BASE + ADC_O_SSFIFO0),
                           &ADCBufferForFft[FFT_SIZE], FFT_SIZE);
        
        MAP_uDMAChannelEnable(UDMA_CH14_ADC0_0);
        MAP_ADCSequenceEnable(ADC0_BASE, 0);
        MAP_ADCIntClear(ADC0_BASE, 0);
        MAP_ADCSequenceOverflowClear(ADC0_BASE, 0);
        MAP_ADCSequenceUnderflowClear(ADC0_BASE, 0);
        MAP_ADCSequenceDMAEnable(ADC0_BASE, 0);
        MAP_ADCIntEnable(ADC0_BASE, 0);
        MAP_IntEnable(INT_ADC0SS0);

//
        // ADC1
        //
        MAP_uDMAChannelTransferSet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *)(ADC1_BASE + ADC_O_SSFIFO0),
                           &ADCBufferForFft, FFT_SIZE);
        
        MAP_uDMAChannelTransferSet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *)(ADC1_BASE + ADC_O_SSFIFO0),
                           &ADCBufferForFft[FFT_SIZE], FFT_SIZE);
        
        MAP_uDMAChannelEnable(UDMA_CH24_ADC1_0);
        MAP_ADCSequenceEnable(ADC1_BASE, 0);
        MAP_ADCIntClear(ADC1_BASE, 0);
        MAP_ADCSequenceOverflowClear(ADC1_BASE, 0);
        MAP_ADCSequenceUnderflowClear(ADC1_BASE, 0);
        MAP_ADCSequenceDMAEnable(ADC1_BASE, 0);
        MAP_ADCIntEnable(ADC1_BASE, 0);
        MAP_IntEnable(INT_ADC1SS0);

  • 0
    TI__Guru*** 135355 points

    Hello Kevin,

    Couple questions here;

    1) Did you modify the startup_ccs.c file to reflect that you have a different ISR for the ADC now?

    2) These two calls are a bit different, can you verify that you have the right addresses here as you are using &ADCBufferForFft for one and &ADCBufferForFft[FFT_SIZE] for the other?

            MAP_uDMAChannelTransferSet(UDMA_CH24_ADC1_0 | UDMA_PRI_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *)(ADC1_BASE + ADC_O_SSFIFO0),
                           &ADCBufferForFft, FFT_SIZE);
        
        MAP_uDMAChannelTransferSet(UDMA_CH24_ADC1_0 | UDMA_ALT_SELECT,
                           UDMA_MODE_PINGPONG,
                           (void *)(ADC1_BASE + ADC_O_SSFIFO0),
                           &ADCBufferForFft[FFT_SIZE], FFT_SIZE);

    I assume you are commenting out all ADC0 setup code?

    Best Regards,

    Ralph Jacobi

  • 0 in reply to Ralph Jacobi
    Prodigy 180 points

    Thank you very much for your help.
    I am always happy when I get help here in the forum.
    1) I am using IAR Embedded Workbench for Arm as IDE.
    I have customized the startup correctly in my opinion.
    Here is my code:

    //*****************************************************************************
//
// startup_ewarm.c - Startup code for use with IAR's Embedded Workbench,
//                   version 5.
//
// Copyright (c) 2013-2020 Texas Instruments Incorporated.  All rights reserved.
// Software License Agreement
// 
//   Redistribution and use in source and binary forms, with or without
//   modification, are permitted provided that the following conditions
//   are met:
// 
//   Redistributions of source code must retain the above copyright
//   notice, this list of conditions and the following disclaimer.
// 
//   Redistributions in binary form must reproduce the above copyright
//   notice, this list of conditions and the following disclaimer in the
//   documentation and/or other materials provided with the  
//   distribution.
// 
//   Neither the name of Texas Instruments Incorporated nor the names of
//   its contributors may be used to endorse or promote products derived
//   from this software without specific prior written permission.
// 
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// 
// This is part of revision 2.2.0.295 of the Tiva Firmware Development Package.
//
//*****************************************************************************

#include <stdint.h>
#include "inc/hw_nvic.h"
#include "inc/hw_types.h"

//*****************************************************************************
//
// Enable the IAR extensions for this source file.
//
//*****************************************************************************
#pragma language=extended

//*****************************************************************************
//
// Forward declaration of the default fault handlers.
//
//*****************************************************************************
void ResetISR(void);
static void NmiSR(void);
static void FaultISR(void);
static void IntDefaultHandler(void);

//*****************************************************************************
//
// External declaration for the interrupt handler used by the application.
//
//*****************************************************************************
extern void uDMAErrorIntHandler(void);
extern void GPIOPortBIntHandler(void);
extern void SysTickIntHandler(void);
extern void ADC0Seq0IntHandler(void);
extern void ADC1Seq0IntHandler(void);

//*****************************************************************************
//
// The entry point for the application startup code.
//
//*****************************************************************************
extern void __iar_program_start(void);

//*****************************************************************************
//
// Reserve space for the system stack.
//
//*****************************************************************************
static uint32_t pui32Stack[512] @ ".noinit";

//*****************************************************************************
//
// A union that describes the entries of the vector table.  The union is needed
// since the first entry is the stack pointer and the remainder are function
// pointers.
//
//*****************************************************************************
typedef union
{
    void (*pfnHandler)(void);
    uint32_t ui32Ptr;
}
uVectorEntry;

//*****************************************************************************
//
// The vector table.  Note that the proper constructs must be placed on this to
// ensure that it ends up at physical address 0x0000.0000.
//
//*****************************************************************************
__root const uVectorEntry __vector_table[] @ ".intvec" =
{
    { .ui32Ptr = (uint32_t)pui32Stack + sizeof(pui32Stack) },
                                            // The initial stack pointer
    ResetISR,                               // The reset handler
    NmiSR,                                  // The NMI handler
    FaultISR,                               // The hard fault handler
    IntDefaultHandler,                      // The MPU fault handler
    IntDefaultHandler,                      // The bus fault handler
    IntDefaultHandler,                      // The usage fault handler
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    IntDefaultHandler,                      // SVCall handler
    IntDefaultHandler,                      // Debug monitor handler
    0,                                      // Reserved
    IntDefaultHandler,                      // The PendSV handler
    SysTickIntHandler,  // The SysTick handler
    IntDefaultHandler,                      // GPIO Port A
    GPIOPortBIntHandler,  // GPIO Port B
    IntDefaultHandler,                      // GPIO Port C
    IntDefaultHandler,                      // GPIO Port D
    IntDefaultHandler,                      // GPIO Port E
    IntDefaultHandler,                      // UART0 Rx and Tx
    IntDefaultHandler,                      // UART1 Rx and Tx
    IntDefaultHandler,                      // SSI0 Rx and Tx
    IntDefaultHandler,                      // I2C0 Master and Slave
    IntDefaultHandler,                      // PWM Fault
    IntDefaultHandler,                      // PWM Generator 0
    IntDefaultHandler,                      // PWM Generator 1
    IntDefaultHandler,                      // PWM Generator 2
    IntDefaultHandler,                      // Quadrature Encoder 0
    ADC0Seq0IntHandler,  // ADC Sequence 0
    IntDefaultHandler,                      // ADC Sequence 1
    IntDefaultHandler,                      // ADC Sequence 2
    IntDefaultHandler,                      // ADC Sequence 3
    IntDefaultHandler,                      // Watchdog timer
    IntDefaultHandler,                      // Timer 0 subtimer A
    IntDefaultHandler,                      // Timer 0 subtimer B
    IntDefaultHandler,                      // Timer 1 subtimer A
    IntDefaultHandler,                      // Timer 1 subtimer B
    IntDefaultHandler,                      // Timer 2 subtimer A
    IntDefaultHandler,                      // Timer 2 subtimer B
    IntDefaultHandler,                      // Analog Comparator 0
    IntDefaultHandler,                      // Analog Comparator 1
    IntDefaultHandler,                      // Analog Comparator 2
    IntDefaultHandler,                      // System Control (PLL, OSC, BO)
    IntDefaultHandler,                      // FLASH Control
    IntDefaultHandler,                      // GPIO Port F
    IntDefaultHandler,                      // GPIO Port G
    IntDefaultHandler,                      // GPIO Port H
    IntDefaultHandler,                      // UART2 Rx and Tx
    IntDefaultHandler,                      // SSI1 Rx and Tx
    IntDefaultHandler,                      // Timer 3 subtimer A
    IntDefaultHandler,                      // Timer 3 subtimer B
    IntDefaultHandler,                      // I2C1 Master and Slave
    IntDefaultHandler,                      // Quadrature Encoder 1
    IntDefaultHandler,                      // CAN0
    IntDefaultHandler,                      // CAN1
    0,                                      // Reserved
    0,                                      // Reserved
    IntDefaultHandler,                      // Hibernate
    IntDefaultHandler,                      // USB0
    IntDefaultHandler,                      // PWM Generator 3
    IntDefaultHandler,                      // uDMA Software Transfer
    uDMAErrorIntHandler,  // uDMA Error
    ADC1Seq0IntHandler,  // ADC1 Sequence 0
    IntDefaultHandler,                      // ADC1 Sequence 1
    IntDefaultHandler,                      // ADC1 Sequence 2
    IntDefaultHandler,                      // ADC1 Sequence 3
    0,                                      // Reserved
    0,                                      // Reserved
    IntDefaultHandler,                      // GPIO Port J
    IntDefaultHandler,                      // GPIO Port K
    IntDefaultHandler,                      // GPIO Port L
    IntDefaultHandler,                      // SSI2 Rx and Tx
    IntDefaultHandler,                      // SSI3 Rx and Tx
    IntDefaultHandler,                      // UART3 Rx and Tx
    IntDefaultHandler,                      // UART4 Rx and Tx
    IntDefaultHandler,                      // UART5 Rx and Tx
    IntDefaultHandler,                      // UART6 Rx and Tx
    IntDefaultHandler,                      // UART7 Rx and Tx
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    IntDefaultHandler,                      // I2C2 Master and Slave
    IntDefaultHandler,                      // I2C3 Master and Slave
    IntDefaultHandler,                      // Timer 4 subtimer A
    IntDefaultHandler,                      // Timer 4 subtimer B
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    0,                                      // Reserved
    IntDefaultHandler,                      // Timer 5 subtimer A
    IntDefaultHandler,                      // Timer 5 subtimer B
    IntDefaultHandler,                      // Wide Timer 0 subtimer A
    IntDefaultHandler,                      // Wide Timer 0 subtimer B
    IntDefaultHandler,                      // Wide Timer 1 subtimer A
    IntDefaultHandler,                      // Wide Timer 1 subtimer B
    IntDefaultHandler,                      // Wide Timer 2 subtimer A
    IntDefaultHandler,                      // Wide Timer 2 subtimer B
    IntDefaultHandler,                      // Wide Timer 3 subtimer A
    IntDefaultHandler,                      // Wide Timer 3 subtimer B
    IntDefaultHandler,                      // Wide Timer 4 subtimer A
    IntDefaultHandler,                      // Wide Timer 4 subtimer B
    IntDefaultHandler,                      // Wide Timer 5 subtimer A
    IntDefaultHandler,                      // Wide Timer 5 subtimer B
    IntDefaultHandler,                      // FPU
    0,                                      // Reserved
    0,                                      // Reserved
    IntDefaultHandler,                      // I2C4 Master and Slave
    IntDefaultHandler,                      // I2C5 Master and Slave
    IntDefaultHandler,                      // GPIO Port M
    IntDefaultHandler,                      // GPIO Port N
    IntDefaultHandler,                      // Quadrature Encoder 2
    0,                                      // Reserved
    0,                                      // Reserved
    IntDefaultHandler,                      // GPIO Port P (Summary or P0)
    IntDefaultHandler,                      // GPIO Port P1
    IntDefaultHandler,                      // GPIO Port P2
    IntDefaultHandler,                      // GPIO Port P3
    IntDefaultHandler,                      // GPIO Port P4
    IntDefaultHandler,                      // GPIO Port P5
    IntDefaultHandler,                      // GPIO Port P6
    IntDefaultHandler,                      // GPIO Port P7
    IntDefaultHandler,                      // GPIO Port Q (Summary or Q0)
    IntDefaultHandler,                      // GPIO Port Q1
    IntDefaultHandler,                      // GPIO Port Q2
    IntDefaultHandler,                      // GPIO Port Q3
    IntDefaultHandler,                      // GPIO Port Q4
    IntDefaultHandler,                      // GPIO Port Q5
    IntDefaultHandler,                      // GPIO Port Q6
    IntDefaultHandler,                      // GPIO Port Q7
    IntDefaultHandler,                      // GPIO Port R
    IntDefaultHandler,                      // GPIO Port S
    IntDefaultHandler,                      // PWM 1 Generator 0
    IntDefaultHandler,                      // PWM 1 Generator 1
    IntDefaultHandler,                      // PWM 1 Generator 2
    IntDefaultHandler,                      // PWM 1 Generator 3
    IntDefaultHandler                       // PWM 1 Fault
};

//*****************************************************************************
//
// This is the code that gets called when the processor first starts execution
// following a reset event.  Only the absolutely necessary set is performed,
// after which the application supplied entry() routine is called.  Any fancy
// actions (such as making decisions based on the reset cause register, and
// resetting the bits in that register) are left solely in the hands of the
// application.
//
//*****************************************************************************
void
ResetISR(void)
{
    //
    // Enable the floating-point unit.  This must be done here to handle the
    // case where main() uses floating-point and the function prologue saves
    // floating-point registers (which will fault if floating-point is not
    // enabled).  Any configuration of the floating-point unit using DriverLib
    // APIs must be done here prior to the floating-point unit being enabled.
    //
    // Note that this does not use DriverLib since it might not be included in
    // this project.
    //
    HWREG(NVIC_CPAC) = ((HWREG(NVIC_CPAC) &
                         ~(NVIC_CPAC_CP10_M | NVIC_CPAC_CP11_M)) |
                        NVIC_CPAC_CP10_FULL | NVIC_CPAC_CP11_FULL);

    //
    // Call the application's entry point.
    //
    __iar_program_start();
}

//*****************************************************************************
//
// This is the code that gets called when the processor receives a NMI.  This
// simply enters an infinite loop, preserving the system state for examination
// by a debugger.
//
//*****************************************************************************
static void
NmiSR(void)
{
    //
    // Enter an infinite loop.
    //
    while(1)
    {
    }
}

//*****************************************************************************
//
// This is the code that gets called when the processor receives a fault
// interrupt.  This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
FaultISR(void)
{
    //
    // Enter an infinite loop.
    //
    while(1)
    {
    }
}

//*****************************************************************************
//
// This is the code that gets called when the processor receives an unexpected
// interrupt.  This simply enters an infinite loop, preserving the system state
// for examination by a debugger.
//
//*****************************************************************************
static void
IntDefaultHandler(void)
{
    //
    // Go into an infinite loop.
    //
    while(1)
    {
    }
}

    2) Sorry I forgot to change the constant. FFT_SIZE is set to 512.
    I wanted to push the data in the same variable. And I start only once the pri and alt transfer. Therefore with the Alt transfer the offset of 512.

    Yes right I always comment everything out to test and look for the error

  • +1 in reply to Kevin Hinrichs
    TI__Guru*** 135355 points

    Hi Kevin,

    I have to say, this perplexed me initially and then floored me with the root cause here. The code looked identically done and I couldn't find any missing steps of your swapping of peripherals. The devil tends to be in the detail with these, but I couldn't find any flaws.

    So I went ahead and started testing the code myself to see the issue first hand and re-created your problem.

    Your ADC0 code does indeed work... but purely by dumb luck!

    The configuration of the uDMA is using the wrong input for all the uDMA channel configuration calls... you are using UDMA_CH14_ADC0_0 instead of the correct UDMA_CHANNEL_ADC0 for all those APIs. ...They just happen to map to 0xE and 14 respectively... which is the same value. So the wrong variable provided the right mapping by coincidence.

    However when you moved to ADC1, your luck ran out, and so the DMA is completely misconfigured.

    Now then, the actual configuration needed here is a bit more complicated than it looks on the surface.

    For ADC1 you switched from UDMA_CH14_ADC0_0 to UDMA_CH24_ADC1_0. Following this logic, if I didn't tell you anything further, I am certain if you understood that UDMA_CHANNEL_ADC0 is the right configuration for your APIs, then you'd naturally use UDMA_CHANNEL_ADC1 instead. However, that will also not work for your purposes. The uDMA is a little tricky to configure because a given channel can only be used for one peripheral. As such, we don't offer #define's for every single peripheral on a given channel for the configuration functions - this is to ensure no one mistakenly tries to put two peripherals on the same channel unknowingly.

    The prior uDMA channel was Channel 14 which maps to UDMA_CHANNEL_ADC0. Meanwhile, UDMA_CHANNEL_ADC1 maps to Channel 15.

    The uDMA channel you have identified to use is Channel 24, and that maps to UDMA_CHANNEL_SSI1RX. Therefore, all your configurations for ADC1 should be changed to use UDMA_CHANNEL_SSI1RX. 

    Now that just sets the uDMA to the right channel... but it will default to SSI1RX. So you need to point Channel 24 to the right peripheral too. That will be done by adding this function call with a familiar input:

        MAP_uDMAChannelAssign(UDMA_CH24_ADC1_0);

    That is how UDMA_CH24_ADC1_0 is used to help point the uDMA to the right peripheral within the channel.

    So to summarize for ADC 1, change every instance of UDMA_CH24_ADC1_0 to be UDMA_CHANNEL_SSI1RX and then add the line of code I provided at the end of your init_uDMA_MIC1 function. This will get the DMA running.

    Now I will note at this point that I saw the overflow issue is still ongoing on my code but I suspect this is because I did not have the buffer swap over code that you likely have in your main code. So I expect that on your end everything should work smoothly at this point as I could configure the ADC buffer was being properly filled with the ADC sample values now.

    Best Regards,

    Ralph Jacobi

  • 0 in reply to Ralph Jacobi
    Prodigy 180 points

    Thanks for your help!
    I would never have found this error.
    I immediately changed all the arguments. And it works now with ADC0 and ADC1.