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TMS570LC4357: Can the MIBSPI5 peripheral [1] pins be used without using the [0] pins?

jimj2713
Expert 2375 points
Part Number: TMS570LC4357

My controller application uses 4 of the 5 MIBSPI peripherals, and all work except MIBSPI5. The external slave is transmit-only, so the ARM-SIMO is unused. The MIBSPI5 CS and clock out all work, and data is received at the DSP pin, but nothing is read from the MIBSPI5 RAM. I noticed that hardware connections to this MIBSPI5 are unique in that the other 3 working MIBSPI all use the [0] selection (CS[0], CLK[0], and SOMI[0]), but the functional pins of the MIBSPI5 only use CS[1], CLK[1], and SOMI[1] -- is this permitted? 

If it is permitted, do I have to do anything special to read data from the SOMI[1], like offset into MIBSPI5 a certain amount?

Thanks,

Jim

  • +1
    Expert 2375 points

    I am looking at parallel-mode as the possible problem/solution to this problem. For this MIPSPI5 peripheral, is it accurate to write that the SOMI[1], SOMI[2], and SOMI[3] pins are only used in parallel mode? If this is true, then the only way to get data in on this SOMI[1] is to use parallel-mode?

    Thanks,

    Jim

  • 0 in reply to jimj2713
    TI__Guru 69591 points

    Hi Jim,

    MIBSPI5 is not different from other MIBSPI's. It is also have the same functionality as other MIBSPI instances.

    SOMI[1], SOMI[2], and SOMI[3] pins are only used in parallel mode?

    Yes these pins are only used in parallel mode.

    My doubt is, are you writing some dummy data from the master?

    If not you should write, because even though the data is only from slave but we should write some dummy data(like 0x00) to SPIDAT if you are using in SPI mode or else we should write one RAM buffer with all zeros and should give it to transfer group and should trigger the group if you are using in Mib SPI Mode. SPI works parallelly i.e. transmission and reception works with full duplex, so to receive data we should write some data other wise Rx shifting will not work.

    --

    Thanks,
    Jagadish.