TMS570LC4357: MEM8: Interconnect Self Test does not set NT_OK and PT_OK bits but ESM 3.12 is not set

Hi Max,

Could you please follow below steps,

1) SL_SelfTest_MemoryInterconnect(MEMINTRCNT_SELFTEST)

2) CPU Reset

3) SL_SelfTest_Status_MemIntrcntSelftest()

4) Verify SDC_STATUS register of ESM for NT_OK and PT_OK bits and they should set.

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Thanks,
Jagdish.

Hi Jagadish,

We are not using the SafeTI functions in our project. Instead we have to implemented the functions ourselves.
We used the SafeTi Library as reference whenever possible.
We tried the follwing is code:

   /* MASK_SOFT_RESET*/
    sl_sdcmmrREG1->SDC_CONTROL = 0x0;

    /** DTC_SOFT_RESET */    
    sl_scmREG1->SCMCNTRL = (sl_scmREG1->SCMCNTRL & (~0xF00U)) | (0xA00U);

    /* Set CPU in IDLE */
    cpu_Idle();

With cpu_Idle:
FUNC    cpu_Idle
    WFI
    BX     LR ;Though not required, to be safe adding branch here
 ENDFUNC cpu_Idle

Reset of CPU due to Interconnect self test is asserted, but we get the result I mentioned above. SDC_STATUS Register shwos 0x0A00 0000

Thank you and best regards,
Max

Hi Jagadish,

I checked the errata sheet and noticed that DEVICE#51 says that the interconnect status register is shifted by 24bits. With that in mind 0x0A00 0000 would be the expected value. BUT after a Power On-Reset (nPORRST) SDC_STATUS already has the value 0x0A00 0000, although it is supposed to be 0x0.

(Q1) What is happening here?

What I do not understand is, which registers are shifted by 24, since writing and reading the SDC_CONTROL Register works as define in the Reference Manual.

(Q2) Can you provide a complete list which registers are affected by this bug?

Thank you and best regards,
Max

Hi Max,

You are right this errata DEVICE#51 will be applicable 

You will get below value in status register if Interconnect self-test is successful

SDC_STATUS: 0x0A000000 - NT_OK(3) & PT_OK(1)

(Q2) Can you provide a complete list which registers are affected by this bug?

This error will be applicable to all the interconnect registers with in the addresses 0xFA000000 through 0xFA00002B.

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Thanks,

Jagadish.

Hi Jagadish,

I am facing one more problem:
After Power On the bits in SDC_STATUS are already:

This contradicts the Technical Reference Manual, which states that the bits should be 0x00000000 after power on.

What could cause this?

Hi Max,

The "Interconnect Self-test" process it self involves the CPU reset right, I mean NT_OK and PT_OK bits are setting after CPU comes out of the reset only 

So can you please try Power ON Reset once?

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Thanks,

Jagadish.

Hi Jagadish,

I have tried multible Power On resets, warm resets, diconnecting the debugger, disconnecting the board from power for some time.
SDC_STATUS is always 0x0A00 0000.

Is this not the case on your silicon?

Hi Max,

I am discussing this with my internal team once and i will get back to you soon.

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Thanks,

Jagadish.

Hi Jagadish,

Any updates on this topic?

Thank you and best regards,
Max