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TMS570LS3137: UART DMA RX VARIABLE SIZE PROBLEM

Part Number: TMS570LS3137

Hi everyone, i need a help to setup dma config.

I have a variable size DMA UART RX. For example, i can get 10 byte or 284 byte. I dont know.

In this situation, how i setup dma config and handle?

and i cant read the dmaRAMREG->WCP[channel] regs. What is the problem? It is a readable reg.

thanks

  • Hi,

    I am working on your issue and i will get back to you by end of the day.

    --

    Thanks,

    Jagadish.

  • Hi ,

    The UART with DMA is not able to change the packet size dynamically.

    So you have to implement some protocol in application level, like the transmitter should needs to tell the receiver about the packet size it is going to send, and receiver can change the DMA packet settings for the new packet size. In this way you can receive variable size of data using UART with DMA.

    --

    Thanks,
    Jagadish.

  • thank for reply,

    i have also one more question.

    what is the difference between dmaRAMREG->WCP[channel] and dmaREG->PBACTC ??

    when i want to read count, if the channel is active WCP is invalid and PBACTC is valid. if the channel is not active PBACTC is invalid and WCP is valid. Right?

    tyhanks

  • Hi,


    I am on leave yesterday, i am verifying your issue now and i will update you soon.

    --
    Thanks,

    Jagadish.

  • Hi ,

    when i want to read count, if the channel is active WCP is invalid and PBACTC is valid. if the channel is not active PBACTC is invalid and WCP is valid. Right?

    That is correct and it is expected behavior, because 

    WCP->CTCOUNT bits will gives remaining frames and elements count in DMA transfer, so these data will be updated after the channel is deactivated, once channel is active these bits are not valid because DMA will transfer so frames and elements will gradually decreases, once the channel is deactivated then these bits will give you the remaining frames and elements of the corresponding channel.

    dmaREG->PBACTC bits will give us current active channel frames and elements transferred count, that means how many frames and elements are transferred from that corresponding active channel. It is the common register for all the channels right, so only active channel transfer count will be reflected into these bits. So we have to read the current active channel number and have to store these data.

    --

    Thanks,

    Jagadish.

  • thanks for help :)

    i got it now