Hi experts,
we noticed that a CPU-Reset triggered by the SW sets the reserved bit0 in SYSESR register: 
The bit can only be reset by a Power On-Reset (nPORRST).
When checking the SYS_ESR for the cause of last reset this leads to SW signalling a failure since this bit is supposed to be 0.
(Q1) Is this a known bug?
(Q2) Should we always ignore bit 0 when checking for the cause of last reset?
Thank you and best regards,
Max
Hi Max,
There is no significant operation for reserved bits, they might be using for some internal purpose with in silicon and some of them might be for future purpose.
We should always ignore the bit status of reserved bits.
(Q1) Is this a known bug?
It is not a bug.
(Q2) Should we always ignore bit 0 when checking for the cause of last reset?
Yes we should always ignore the reserved bits
And in this register to identify the reset cause the following bits should be use
Other than above bits remaining bits are not useful.
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Thanks,
Jagadish.
