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TMS570LS3137: Expected failure rate of PCB soldering

Part Number: TMS570LS3137

Hi,

The summary sheets of the configurable FMEDA you issued includes a certain total (raw) FIT rate for the package apart from the die-related permanent and transient failure rates. (The package permanent FIT rate depends on whether TI PBGA or TI QFP is set of course.)

Does this failure rate include the attachment (soldering) to a generic multilayer FR4 board? If not, then can you please advise an estimation of the expected failure rate of the soldering for both BGA and QFP?

Thanks,

Tamas

  • Hi Tamas,

    TI uses the IEC/TR 62380 model to estimate package FIT rate for the BGA package used on the Hercules family. The IEC/TR 62380 package model is primarily concerned with wear-out due to thermal expansion between the package and the PCB.

    TI silicon technologies are designed with a high degree of margin to the wear out failure mechanisms respected in IEC/TR 62380; most applications will not approach the wear-out limits within product lifetime.

  • Hi,

    Thank you for this answer. You wrote the "between the package and the PCB". For clarity, you mean this FIT rate figure characterizes the attachment (soldering and soldering pads) to the PCB (with a basic assumption that the PCB is a usual multilayer FR4 (with some GND layer under the BGA) ), don't you?

    Thanks,

    Tamas

  • Hi Tamas,

    The IEC/TR 62380 IC failure rate can be modeled as sum of the die, package and electrical overstress (EOS) related failure rates:

    1. The die-related failure rate formula includes terms for IC type and IC technology, transistor count, thermal mission profile, junction temperature, and operating and non-operating lifetime.

    2. The package-related failure rate formula includes terms for mechanical stress caused by thermal expansions, thermal cycles, thermal mission profile, package type and package materials.

    3. The EOS failure rate formula includes terms for specific systems with an external interface and electrical environment.

    The IEC/TR 62380 accounts for the solder joints, but I don't know the details. Please refer to the IEC/TR 62380 standard for more information regarding the failure rate calculation.

  • Hi,

    Thank you for this answer. If I understand you correctly, the failure rate you give covers the potential on-chip, bonding and BGA substrate related failures (i.e. problems in the package), but doesn't address the BGA substrate - PCB attachment (balls, soldering).

    1. Can you please advise a method for estimating a failure rate of the substrate - PCB attachment (balls, soldering)?

    2. A more tricky question: in most reports on BGA reliability, the problem that the thermal cycles cause is a cracking between the substrate and a soldering ball (in contrast to cracking between a ball and the PCB). The balls themselves actually belong to the BGA package, accordingly such cracks between the BGA substrate and a ball also belong to package reliability to a certain degree. How does the package FIT estimation handle the potential cracks between the balls and the BGA substrate?

    Kind regards,

    Tamas

  • Hi Tamas,

    I don't have a answer to your question #1.

    For question #2, the balls, substrate, and their interface are considered as permanent faults and covered by the failure rate of MCY packaging. 

    Please let me your email, so I can forward your question to other experts.

  • Hi,

    My email is tfenyvesi@sensata.com.

    Looking forward to having any answers regarding both topics,

    Kind regards,

    Tamas

  • Thanks

    1. Can you please advise a method for estimating a failure rate of the substrate - PCB attachment (balls, soldering)?

    From the FMEDA, Pin level tailoring page contains the diagnostic coverage for all the pins. The diagnostics includes the information redundancy techniques, I/O loopback, or monitored by another module for example PWM signal can be monitored by eCAP or N2HET etc. If the ball loses contact to the PCB, the diagnostics will get failed. ANother example,  a failure on the DCAN RX (receive) pin can be detected by the diagnostics such as "CAN14 - CAN Protocol CRC in Message".  The failure of substrate-PCB attachment can be detected with the diagnostics by the application.

  • Hi,

    I know, the role of safety mechanisms is to mitigate failures incl. soldering and other hw problems. The safety mechanisms may have low (60%) to high (99%) diagnostic coverages in ISO 26262 and some other FuSa standards.

    The Hercules processors are advertised for 26262 / ASIL D and 61508 / SIL 3 level. ASIL D offers only a 10 FIT budget for the whole equipment. If the package-related total failure rate is already xx FIT and the ball - PCB soldering is not even included (i.e. it's additional xx FIT), then the total failure rate is already high even considering safety mechanisms with high diagnostic coverage.

    One can say the safety-related FIT rate is lower than the total FIT, since not all ports/balls are safety-related. That's true for die-related and for EOS failures, but unfortunately doesn't apply to cracks in soldering, I afraid. If a soldering breaks then the mechanical stress on the adjacent solderings increases, which can lead to spreading of the cracks. In this regard, even the balls with electrically non-safety function are actually safety-related in mechanical term. In FuSa's perspective, the soldering cracks seem dependent failures (namely cascading failures in ISO 26262 terminology).

    That's why my question focuses on mechanical aspects of the PCB attachments rather than sw workarounds. ASIL D / SIL 3 is very demanding: I'd like to be sure for that the reliability of the solderings still allows a certain ASIL / SIL level. This is more critical for BGA and seems fine with gull-wing QFP.

    Kind regards,

    Tamas 

  • Hi Tamas,

    Let me check with our safety expert to se of the ball-PCB soldering is included in our failure rate calculation.