• State TI Thinks Resolved
  • Locked Locked
  • Replies 5 replies
  • Answers 2 answers
  • Subscribers 30 subscribers
  • Views 409 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

Original question:

TMS570LC4357: Regarding Decoupling Capacitors

TMS570LS3137: VCCPLL quiescent / dynamic current and capacitance recommendations

Mike Hudson
Prodigy 10 points
Part Number: TMS570LS3137


Am performing a design analysis and am looking for more detailed  information about PLL current draw.  The design has a filtered PLL supply - filtered from the VCC supply.

The data sheet (SPNS162C) has a table containing VCC + VCCPLL current ( I assume they are added ) in section 5.7.

Would it be possible to get current for VCCPLL only for the same conditions.  Alternately, a graph of VCCPLL current vs input and output clock frequencies would be great.

I have also seen mentions in this forum, I believe, for decoupling recommendations.  But there were no more detail given than a recommendation for one 0.1uF cap per power pin that I think is also in the data sheet.  But in case there have been any TI guidance documents created in the interim, can you point the way to such a document?

Thanks for any help

  • 0
    TI__Guru**** 197526 points

    Hi Mike,

    The specification only provides the current for VCC and VCCPLL combined. The PLL current is typically under 10mA, but because there are two PLLs, the pin could see 20mA.

    A ferrite is useful between the regulator and the VCCPLL in if you have a very noisy environment. If you see very small noise on your circuit, there is no need to add a ferrite filter.

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Hi and thanks for your answer but I really need to know worst case or maximum PLL current draw.  It would also help to know quiescent current and both average and peak dynamic currents.

    Best Regards

  • 0 in reply to Mike Hudson
    TI__Guru**** 197526 points

    Hi Mike,

    My measurement shows that the current at idle (CPU suspends at a breakpoint in main()) is around 2.3mA (PLL1=PLL2=180MHz), and the current when performing SRAM reading and writing is around 3.2mA.

    I did measurement on TMS570LS3137HDK which has a small resistor on VCCPLL power supply. 

  • 0 in reply to QJ Wang
    Prodigy 10 points

    Thank you again for your answer.  I had looked at development boards before but do not remember seeing the schematic / design files.  But I saw them this time.  And the schematic provides a context for your measurements.  Also the VCCPLL of the HDK is a filtered version of the core VCC.  So your response is helpful.  By example, it contains decoupling recommendations and that was one of my original questions.  But it would be even better if there was more detail on PLL current consumption.  It looks like I may have to perform my own measurements on our design.

    Best Regards

  • 0 in reply to Mike Hudson
    TI__Guru**** 197526 points

    Hi Mike,

    We don't have the data of PLL current consumption. Please measure the power consumption on your own board.