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MCU-PLUS-SDK-AM263X: AM263x cc EVM SBL

carmel gorali
Prodigy 50 points
Part Number: MCU-PLUS-SDK-AM263X
Other Parts Discussed in Thread: SYSCONFIG

Hi!

using AM263x I want to set Qualifier to a bank of GPIO's. 

Is there a table that list the GPIO's according to their bank/group ?

I see in the TRM that there are 16pins per bank, and there are 9 banks per module...

Thanks

Carmel

  • 0
    TI__Expert 7585 points

    Hi Carmel

    Could you specify why do you need the Qualifier option.

    Qualifier Option is present for every Pin in the sysconfig as shown here:

    And the GPIO Banks are for Xbar Interrupt configuration.

    Regards

    Sri Vidya

  • 0 in reply to Sri Vidya Gunturi
    Prodigy 50 points

    Hi!

    I want to filter the input signal.

    I see there are the following registers:

    #define CSL_IOMUX_QUAL_GRP_0_CFG_REG (0x00000248U)
    #define CSL_IOMUX_QUAL_GRP_1_CFG_REG (0x0000024CU)
    #define CSL_IOMUX_QUAL_GRP_2_CFG_REG (0x00000250U)
    #define CSL_IOMUX_QUAL_GRP_3_CFG_REG (0x00000254U)
    #define CSL_IOMUX_QUAL_GRP_4_CFG_REG (0x00000258U)
    #define CSL_IOMUX_QUAL_GRP_5_CFG_REG (0x0000025CU)
    #define CSL_IOMUX_QUAL_GRP_6_CFG_REG (0x00000260U)
    #define CSL_IOMUX_QUAL_GRP_7_CFG_REG (0x00000264U)
    #define CSL_IOMUX_QUAL_GRP_8_CFG_REG (0x00000268U)
    #define CSL_IOMUX_QUAL_GRP_9_CFG_REG (0x0000026CU)
    #define CSL_IOMUX_QUAL_GRP_10_CFG_REG (0x00000270U)
    #define CSL_IOMUX_QUAL_GRP_11_CFG_REG (0x00000274U)
    #define CSL_IOMUX_QUAL_GRP_12_CFG_REG (0x00000278U)
    #define CSL_IOMUX_QUAL_GRP_13_CFG_REG (0x0000027CU)
    #define CSL_IOMUX_QUAL_GRP_14_CFG_REG (0x00000280U)
    #define CSL_IOMUX_QUAL_GRP_15_CFG_REG (0x00000284U)
    #define CSL_IOMUX_QUAL_GRP_16_CFG_REG (0x00000288U)
    #define CSL_IOMUX_QUAL_GRP_17_CFG_REG (0x0000028CU)

    What are they used for?

  • +1 in reply to carmel gorali
    TI__Expert 7585 points

    Hi Carmel

    These are for programming the qualifier clock count per sample for a GPIO group.

    There are total 144 GPIO pins and to configure qualifier clock setting, these GPIOs are divided into 18 groups, with 8 GPIOs in each group representing certain feature.

    GPIO clock frequency is 200 MHz and you can configure sampling frequency using the QUAL_GRP registers.

    For more information: 

    User guide AM263x Sitara Processors Technical Reference Manual Register Addendum   15 Mar 2022

    Regards

    Sri Vidya