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TMS570LC4357: MPU overlay problem

li xy
Intellectual 355 points
Part Number: TMS570LC4357

Hi all

    1.There is a background region including the whole SRAM from 0x0800_0000 to 0x0807_FFFF.  The attributes of this region is "MPU_PRIV_RW_USER_RO_NOEXEC | MPU_NORMAL_OIWBNOWA_NONSHARED".

    2. There is  a region 6 which from 0x0800_0000 to 0x0801_0000. The attributes of this region is "MPU_PRIV_RW_USER_RO_NOEXEC | MPU_NORMAL_OIWBNOWA_NONSHARED".

    3. Also, I have a overlay region 4 which from 0x0800_0000 to 0x0803_0000, The attributes of this region is "MPU_PRIV_RW_USER_RO_NOEXEC | MPU_NORMAL_OIWBNOWA_SHARED".

   The question is that when I change region 6 from nonshared to shared, the mcu  will keep rebooting. but whty?

Best Wish

Li

  • 0
    TI__Guru**** 196776 points

    Hi,

    For overlapping MPU regions, the attributes and permissions for region with higher priority determines attributes and permissions for memory access to the overlapping region. 

    Region 6 has higher priority than region 4. 

    What operation causes the device reset, memory read, memory write, or code execution from SRAM?

  • 0 in reply to QJ Wang
    TI__Guru**** 196776 points

    "MPU_NORMAL_OIWBNOWA_NONSHARED"  --> "MPU_NORMAL_OIWBNOWA_SHARED"

    Shareable has a specific meaning --> shared by several processors. The TMS570 device has lockstep configuration, and the 2nd CPU core is a checker/ diagnostic channel and it does not act independently. I think the shared and non-shared doesn't make any difference on TMS570 devices.

  • 0 in reply to QJ Wang
    Intellectual 355 points

    Thank you for your answers. I used to ask a related question about what's meanning of sharable and non-sharable. I remember that if this region is shared, the all bus masters can access at same time. The master bus here which means DMA, CPU, DMM,EMAC,etc but not another CPU.

  • 0 in reply to QJ Wang
    Intellectual 355 points

    "What operation causes the device reset, memory read, memory write, or code execution from SRAM?"

    The project is based on LWIP, the reset reason maybe the DMA transform. There is a huge buf which lay on region 6 and region 4. So parts of this buf could be shared and the reset maybe not.

    When I debug this code, I find that I can receive parts of correct data but the other parts are zero. In this case, I think maybe something with the configuration of MPU

  • 0 in reply to li xy
    TI__Guru**** 196776 points

    Hi xy,

    Please read the description in ARM TRM: DDI0460D_cortex_r5_r1p2_trm.pdf

    The shared or no shared means between the processors, rather than the bus maters in the devices. 

  • 0 in reply to QJ Wang
    TI__Guru**** 196776 points

    If DMA or CPU accesses an implemented memory location or no-accessable memory location, it will generate data abort rather than device reset. Does your dabort handler reset the device intentionally by writing value (not 0x1) to RESET[1:0] of SYSECR?

    Can you add a breakpoint in your dabort handler to check the value of data abort status and address registers (DFSR, DFAR)?

  • 0 in reply to QJ Wang
    Intellectual 355 points

    Thank you for your answer.

    Could you please give me an example about what are an implemented memory or no-accessable memory?

    In my  mind, the buf is in SRAM, i think the whole region is accessable.

  • 0 in reply to li xy
    TI__Guru**** 196776 points

    The un-implemented memory is the memory location which is out of the valid range. No-accessable memory I mean is the memory locations which is configured as no access in user mode and your code execution is under code mode. 

    Does your code generate abort after changing to MPU region 6 from nonshared to shared?

  • 0 in reply to QJ Wang
    TI__Guru**** 196776 points

    Hi,

    SHAREDRAM (RW) : origin=0x0807C000 length=0x00004000

    #pragma SET_DATA_SECTION(".sharedRAM")
    unsigned int myValue= 28;
    uint8_t TX_DATA[8] = {0,1,2,3,4,5,6,7};
    uint8_t RX_DATA[8] = {0,2,4,6,8,9,1,3};
    #pragma SET_DATA_SECTION()

    I changed the MPU setting of MPU region 15 as you did, and I everything works fine. TX_DATA[] and RX_DATA[] are mapped to this region.

  • 0 in reply to QJ Wang
    Intellectual 355 points

    what about setting region 15 to non-shared?

  • +1 in reply to li xy
    TI__Guru**** 196776 points

    Hi Li,

    li xy said:
    The question is that when I change region 6 from nonshared to shared, the mcu  will keep rebooting. but whty?

    The MPU can generate background faults, permission faults, and alignment faults. When a fault occurs, the memory access or instruction fetch is  synchronously aborted, and a Prefetch Abort or Data Abort exception is taken as appropriate. ALl those fault will not cause device re-boot.