AM2634: ePWM2 SYNC-IN SYNC-OUT Option. How does it need to be configured?

Hi,

I'm looking into this and will get back with you shortly.

Regards,
Frank

Hi Markus,

ngrkus said:

I tried to synchronize ePWM0 with ePWM1. However no luck so far.

For details on EPWM synchronization, please see the AM263x TRM (https://www.ti.com/lit/pdf/spruj17):

• 7.4.5.5.3.3 Time-Base Counter Synchronization
• 7.4.5.5.3.4 ePWM SYNC Selection

MCU+SDK provides methods to configure EPWM synchronization using either Sysconfig or API functions.

In the Sysconfig EPWM configuration, see the following EPWM time base options:

• Sync In Pulse Source
• Sync Out Pulse
• Counter Mode After Sync
• Enable Phase Shift Load
• Phase Shift Value

For SDK API functions, see:

• https://software-dl.ti.com/mcu-plus-sdk/esd/AM263X/08_03_01_06/exports/docs/api_guide_am263x/group__DRV__EPWM__MODULE.html#ga01732633314ae56d00db50a586015d15
• https://software-dl.ti.com/mcu-plus-sdk/esd/AM263X/08_03_01_06/exports/docs/api_guide_am263x/group__DRV__EPWM__MODULE.html#ga60255e44454d5ca61145e971abd237ee

ngrkus said:

Now a good idea and a little help is need to get fs3 phase aligned as well.

I don't see a simple way to do this using EPWM synchronization and SOCA/B.

If EPWMx is sync'd EPWM0, it will load TBPHS into TBCTR on the SyncI event. This ties the EPWMx period to that of EPWM0. Hence, no event within the EPWMx period can be used to generate SOCA/B with 1/20th the frequency of the EPWM0 SOCA.

EPWMx SOCA output generation can be pre-scaled by up to 15 (see the TRM, 7.4.5.11.1 Operational Overview of the ePWM Event-Trigger Submodule), but this isn't enough scaling for 1/200th of the EPWM0 SOCA.

I've looped some colleagues with more expertise on this topics in case they have some more ideas.

Regards,
Frank

Hi Frank,

a simple example showing that the sync-in sync-out options between ePWM units work would help. I did check the generated code within the "ti_drivers_open_close" section. I use ePWM1 as the fs3 1KHz signal. I want to use this event to re-sync ePWM0 which is producing the 200KHz SOCA signal and the 50KHz SOCB signal.

According to the figure 7-109 on page 409 in the TRM this should work. The generated c-code does the following:

... ePWM1...

EPWM_enableSyncOutPulseSource(CONFIG_EPWM1_BASE_ADDR, EPWM_SYNC_OUT_PULSE_ON_CNTR_ZERO);

...ePWM0...

EPWM_setSyncInPulseSource(CONFIG_EPWM0_BASE_ADDR, EPWM_SYNC_IN_PULSE_SRC_SYNCOUT_EPWM1);

Additionally I did map all SOCx to the output pin GPIO-Pin-R3 in order to scope probe the 'triggers'. However I get the impression that there is no sync-in function happening for ePWM0 the way it is showcased in figure 7-109 in the TRM.

Ch1 (Green) is a 1KHz input sine wave 3Vpp

Ch2 (Magenta) is the DAC output. The ADC0 is being triggered every 4th 200KHz SOCA resulting in being a 50 KHz trigger. As before those two triggers originating from ePWM0 are phase aligned.

Ch3 (Blue) is showing the 200 KHz triggers. Suddently the 1KHz from ePWM1 appears in between 2 consecutive 200KHz triggers. However it has no influence. What I would have expected is a reload according to figure 7-109 in the TRM.

Any comments on this? Is there an example I can probe using the AM2634-CC that is demonstrating the SYNC-IN SYNC-OUT feature?

Thank's

Markus

Hey Markus,

Thank you for your patience here. I believe the Sync-In to Sync-Out connectivity option is unavailable in the AM263x device. I am looping in our design and SW experts to confirm and decide if an alternative method is available for synchronizing these 3 epwm signals.

I also wanted to make you aware of the TMDSHSECDOCK that is compatible with the AM263x Control Card. The Control Card docking station provides access to a majority of the remaining pins including additional GPIO signals.

https://www.ti.com/tool/TMDSHSECDOCK

Best Regards,

Zackary Fleenor

Hi Zackary,

I would have the same question than Markus, could you confirm that it is really not available on AM263x device?

Thank you.

Br, Nicolas

Markus, Nicolas,

I have a couple of solutions for this issue. I'll share details later today.

Regards,
Frank

Hi Markus,

Sorry for the delayed response.

I have an example which provides the behavior you've described for your use case: synchronous ADC SOC events at fs1 (200 kHz), fs2 (50 kHz), and fs3 (1 kHz) with a fixed phase relationship.

This example uses AM263x MCU+SDK 08.03.01.06 and runs on the AM263x CC (https://www.ti.com/tool/TMDSCNCD263) + HSECDOCK (https://www.ti.com/tool/TMDSHSECDOCK).

The example is a modified version of the SDK EPWM HR duty cycle example: https://software-dl.ti.com/mcu-plus-sdk/esd/AM263X/08_03_01_06/exports/docs/api_guide_am263x/EXAMPLES_DRIVERS_EPWM_HR_DUTY_CYCLE.html

First, I want to say that it's possible to route EPWM SOCA and SOCB signals through Control SS XBARs to pins which can be observed on the HSECDOCK.  I used these XBAR connections to route the following signals to AM263x pins to HSECDOCK:

• OUTPUTXBAR1 : EPWM0_SOCA
• OUTPUTXBAR2 : EPWM0_SOCB
• OUTPUTXBAR3 : EPWM1_SOCA

Although I don't use this XBAR configuration in this example, it's also possible to route EPWM SYNCO signals through Control SS XBAR. For example, the EPWM1 SYNCOUT signal can be routed using XBARs as follows:

• EPWM_SYNCOUT_XBAR_0 : EPWM1_SYNCOUT
• OUTPUTXBAR4 : EPWM_SYNCOUT_XBAR0

The example involves simultaneously enabling EPWM0 and EPWM1 TBCTR by writing to CONTROLSS_CTRL_EPWM_CLKSYNC. This register contains the ETPWM clock sync for each EPWM instance, where each bit position corresponds to an EPWM instance. If TBCTR for both EPWMs are simultaneously enabled, the EPWM TBCTR phases are aligned. Hence, the resulting SOC signals from each EPWM are also aligned.

Below are logic analyzer captures for the EPWM0/1 SOC signals with the desired frequencies at different zoom levels.

The EPWM0 SOCA, SOCB and EPWM1 SOCA signals remain synchronized, with only 20 nsec delay from the rising edge of EPWM0 SOCA/SOCB and the rising edge of EPWM1 SOCA.

I've attached the full CCS project and source code in the zip file below. 

A few notes on the example:

1) Write to CONTROLSS_CTRL_EPWM_CLKSYNC

• When EPWM0 and EPWM1 are enabled in Sysconfig, the generated Sysonfig code enables TBCTR for each EPWM separately. See ti_drivers_config.c:System_init(). Since we want to write to CONTROLSS_CTRL_EPWM_CLKSYNC once, we need comment out the call to SOC_setEpwmTbClk() in the template code used by Sysconfig for generating System_init(). The template code is contained in file <SDK>\source\drivers\.meta\epwm\templates\epwm_init.c.xdt. I've attached an example of the updated file below.

/* finally we initialize all peripheral drivers */
/* EPWM */
{
    /* Enable time base clock for the selected ePWM */
    SOC_setEpwmTbClk(0, TRUE);
    SOC_setEpwmGroup(0, 0);
    SOC_setEpwmTbClk(1, TRUE);
    SOC_setEpwmGroup(1, 0);
}              

• I added code to epwm_hr_duty_cycle_main() to write CONTROLSS_CTRL_EPWM_CLKSYNC:
  • Start of function: write 0
  • Before while() loop: write 0x3 to enable EPWM0 and EPWM1.

2) Control SS OUTPUTXBAR configuration

There is a bug in AM263x MCU+SDK 08.03 (MCUSDK-7342) which only allows a single OUTPUTXBAR to be configured from Sysconfig. I configured OUTPUTXBAR1 using Sysconfig, but to configure OUTPUTXBAR2,3,4 (and associated pin mux) I had to add code to epwm_hr_duty_cycle_main(). This bug will be fixed in SDK release 08.04.

I'm working on a second example that uses the EPWM1 SYNCO to EPWM0 SYNCI mechanism. I plan to have this completed soon and will share it with you when it's done.

Regards,
Frank

/cfs-file/__key/communityserver-discussions-components-files/908/epwm_5F00_hr_5F00_duty_5F00_cycle_5F00_sync0_5F00_am263x_2D00_cc_5F00_r5fss0_2D00_0_5F00_nortos_5F00_ti_2D00_arm_2D00_clang.zip

/cfs-file/__key/communityserver-discussions-components-files/908/epwm_5F00_init.c.xdt

Hi Frank,

this sounds good. I will set it up here on my setup and let you know the outcome.

br

Markus

Hi Markus,

I have a second example which uses the EPWM SYNCO - SYNCI feature. The example provides the behavior you've described for your use case. The example uses the same HW and SDK as the first example.

This is a brief outline of the EPWM configuration.

EPWM0

• frequency: 200 kHz
• Up-down count mode
• Count up after sync
• Enable phase shift load
• Phase Shift Value: 0
• Sync-in Source is EPWM sync-out signal
• ADC SOCA trigger enabled
  • trigger source: time-base counter equal to zero
  • trigger event count: 1 event generates interrupt
  • trigger event count init enabled
  • trigger event count init value: 0
• ADC SOCB trigger enabled
  • trigger source: time-base counter equal to zero
  • trigger event count: 4 events generates interrupt
  • trigger event count init enabled
  • trigger event count init value: 3

EPWM1

• frequency: 1 kHz
• Up-down count mode
• Sync Out Pulse: Counter zero event generates EPWM sync-out pulse
• ADC SOCA trigger enabled
  • trigger source: time-base counter equal to zero
  • trigger event count: 1 event generates interrupt

I've attached the full CCS project and source code in the zip file below.

When you run the example, please be sure to revert the changes to epwm_init.c.xdt from example #1.

I have one concern for this example. For the SOCB trigger, the SYNCI event is used to clear the event counter and increment the event counter (indirectly via TBCNT becoming zero on sync). Hence there is a possible race condition between the event counter clear and increment. I'm developing a third example to avoid any possible race condition. I'll share this with you when it's complete.

Regards,
Frank

Logic analyzer capture at first EPWM1 SYNCOUT

Logic analyzer capture of EPWM0 SOCA,B & EPWM1 SOCB

epwm_hr_duty_cycle_sync1_am263x-cc_r5fss0-0_nortos_ti-arm-clang.zip

Hi Frank,

I did implement proposal 1 from you in my context where I do include the ADC, DAC and one EDMA channel. It seems to work. However, if for example I do restart the application within the debugger environment I do get a phase jump of fs3 with respect to fs1 and fs2.

I need to press the reset button on the control card in order to get rid of this phase shift. The configuration always works after a reset. A 2nd time or more I do get the phase shift.

This is true for version one of you proposed solution where the EPWM units are not synced to each other but the clock is being enabled by an ATOMIC write to the register you mentioned.

Therefore something like 'reset all EPWM units' is needed.

br

Markus

The scope shot above everything is good and in phase. After a reset.

Yellow (Ch1) is the DAC output. The input is a 5KHz Sine wave on ADC0_AIN0

The ADC trigger in this context is the 50 KHz fs2 signal shown in blue (Ch3)

Ch2 is fs1 the 200 KHz signal

Ch4 (Green) is fs3. All good so far.

Reload the image through the debugger a phase jump results. Will need to investigate further why this happens ...

The 1KHz trigger fs3 is not in the same phase position as before ...

Hi Markus,

Did you try example #2 to see if it exhibits the issue you're observing?

I developed a 3rd example which, like example #2, uses the EPWM SYNCO - SYNCI feature.

This is a brief outline of the EPWM configuration:

EPWM0

• EPWM Time Base
  • Time Base Clock Divider: /1
  • High Speed Clock Divider: /1
  • Time Base Period: 999
  • Counter Mode: Up-count mode
  • Enable Phase Shift Load: enabled
  • Sync In Pulse Source: Sync in source is EPWM1 sync-out signal
  • Phase Shift Value: 500
• EPWM Event Trigger
  • ADC SOCA trigger enabled
    • trigger source: time-base counter equal to zero
    • trigger event count: 1 event generates interrupt
    • trigger event count init enabled
    • trigger event count init value: 0
  • ADC SOCB trigger enabled
    • trigger source: time-base counter equal to zero
    • trigger event count: 4 events generates interrupt
    • trigger event count init enabled
    • trigger event count init value: 0

EPWM1

• EPWM Time Base
  • Time Base Clock Divider: /4
  • High Speed Clock Divider: /1
  • Time Base Period: 49999
  • Counter Mode: Up-count mode
  • Sync Out Pulse: Counter equal to CMPC generates EPWM sync-out pulse
• EPWM Counter Compare
  • CMPC: 125 (500/4 because of time base clock divider)
• EPWM Event Trigger
  • ADC SOCA trigger enabled
    • trigger source: time-base counter equal to zero
    • trigger event count: 1 event generates interrupt

Unlike example #2, I don't see a possible HW race condition in the EPWM0 Event-Trigger SOCB Pulse Generator. The SYNCI event is driven by EPWM1 TBCTR=CMPC, while the event counter increment is driven by EPWM0 TBCTR=0.

I've attached the full CCS project and source code in the zip file below.

I tried halting (Alt-F8), resetting (Ctrl+Shift+R) and resuming the CPU (F8), and the PWM waveforms look correct. I also tried halting (Alt-F8) and Restarting (Run->Restart), and again the PWM waveforms look correct.

Regards,
Frank

Logic analyzer capture at first EPWM1 SYNCOUT

Logic analyzer capture of EPWM0 SOCA,B & EPWM1 SOCB

epwm_hr_duty_cycle_sync5_am263x-cc_r5fss0-0_nortos_ti-arm-clang.zip