TM4C1294NCPDT: UART RX FIFO trigger level and RX FIFO EMPTY FLAG behavior

Hi,

  If the RXFE flag remains 1, it means that the receive FIFO is empty.

  If you look at the uart_echo example, it uses UARTCharsAvail() as the condition to keep reading the RXFIFO until it is empty. Why wouldn't you try using UARTCharsAvail instead of relying on RXFE?

void
UARTIntHandler(void)
{
    uint32_t ui32Status;

    //
    // Get the interrrupt status.
    //
    ui32Status = MAP_UARTIntStatus(UART0_BASE, true);

    //
    // Clear the asserted interrupts.
    //
    MAP_UARTIntClear(UART0_BASE, ui32Status);

    //
    // Loop while there are characters in the receive FIFO.
    //
    while(MAP_UARTCharsAvail(UART0_BASE))
    {
        //
        // Read the next character from the UART and write it back to the UART.
        //
        MAP_UARTCharPutNonBlocking(UART0_BASE,
                                   MAP_UARTCharGetNonBlocking(UART0_BASE));

        //
        // Blink the LED to show a character transfer is occuring.
        //
        MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, GPIO_PIN_0);

        //
        // Delay for 1 millisecond.  Each SysCtlDelay is about 3 clocks.
        //
        SysCtlDelay(g_ui32SysClock / (1000 * 3));

        //
        // Turn off the LED
        //
        MAP_GPIOPinWrite(GPIO_PORTN_BASE, GPIO_PIN_0, 0);
    }
}

Hi Charles,

I'm still debugging but appears I'm reading the RX FIFO faster than the filling rate. This is why the empty flag is matching the threshold level. I'll hold the receive state, waiting for the following RX FIFO interrupts until I have a time out interrupt to process all package received.

I'll test it on the next hours...

Hi Richard,

  I did some testing but failing to understand something myself. If I enable FIFO and set the FIFO level to 2/8 or even 7/8, the interrupt will trigger immediately as soon as I send one byte. The FIFO is 16bytes deep. 2/8 means 4 bytes or 14 bytes for 7/8. It does not wait for 4 bytes to trigger the interrupt but only after one byte instead. I don't know if you notice the same. There may be a hardware issue that I cannot explain. 

Yes, the FIFO threshold level to trigger the interrupt is working. Here is a fragment of the initialization code I'm using:

MAP_UARTFIFOLevelSet(UART_PORT_BASE, UART_FIFO_TX1_8, UART_FIFO_RX2_8); // Sets the TX (2bytes) and RX (4bytes) FIFOs interrupt threshold. 
MAP_UARTFIFOEnable(UART_PORT_BASE); // Enable FIFO. TX and RX FIFO.

MAP_UARTTxIntModeSet(UART_PORT_BASE, UART_TXINT_MODE_EOT); // TX interrupt will trigger based on END of Transmission.

MAP_IntEnable(INT_UART2);

Hi Richard,

  Glad that you solve the problem with a workaround. I will also try your code snippet to see if I can even get the interrupt to trigger per programmed FIFO threshold level.