Hi all:
In my project, we use RTIFRC0 as system tick and I think RTIFRC0 is based on GCLK(300MHZ).
However, when I changed the HCLK and VCLK1,2,3, I find the counter speed of RTIFRC0 is changed as well.
So what is the clock source of RTIFRC0?
Best Wish
Li
Hi Li,
We can also select VCLK as RTI clock source, and by default after reset the RTI clock source is VCLK only.
You can also find same thing in HalCoGen as well
As you can see in above image the post RTI1 source is selected to VCLK, that means when ever you change the VCLK1 frequency then it also changes the clock applied to the RTI module.
Here you can also select post source to Pre source as below
after that you can select the required clock source at pre source(i.e. OSC or PLL1 or PLL2 etc), in this case changing VCLK dividers won't effect the RTI clock.
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Thanks,
Jagadish.
