AM2732: Processor Stall during test And the target did not respond to the “break“ request which sent from debugger

Feng Pei

Part Number: AM2732

During durability test, we have a crash situation, seems like the kernel hung, the internal data bus can not be accessed, the performance is as follows:

1. The whole chip is stuck without outgoing packets, and the software cannot run

2. JTAG can connect to the debugger, but it does not respond to any debugging instructions, displays the chip in "running" state, can not "break", and cannot show register, peripheral and memory data information at all

3. This phenomenon never occurs before Cache is enabled, but occasionally occurs after L2 Cache is enabled.

I want to know what causes this happens

Thank you

over 3 years ago

0 Feng Pei over 3 years ago

Prodigy 20 points

Sorry， The problem occurs in the R5Fcore

0 Frank Livingston over 3 years ago in reply to Feng Pei

TI__Mastermind 29638 points

Hi Feng,

Can you please describe your system a bit more?

What hardware are you using? A TI EVM or a custom board?

What software are you using? Are you using the AM273x MCU+SDK? If so, which version?

Feng Pei said:
kernel hung

What kernel are you using?

Feng Pei said:
JTAG can connect to the debugger, but it does not respond to any debugging instructions

How do you know you can connect JTAG? When you say debugging instructions, do you mean commands from the CCS GUI?

Feng Pei said:
without outgoing packets

Does this mean the system uses Ethernet? From which interface are the packets produced?

Feng Pei said:
This phenomenon never occurs before Cache is enabled, but occasionally occurs after L2 Cache is enabled

How is the Cache enabled? What function is called and where/when is it called? Is the Cache ever disabled after being enabled? Does the crash occur immediately after calling the function or after some time?

Regards,
Frank

0 Feng Pei over 3 years ago in reply to Frank Livingston

Prodigy 20 points

Hi Frank：Thank you for your reply.

Use Custom Board；Mcal version 1.4.0.0 + Autosar OS；Autosar OS running on R5F core； ETH has already been disable. CAN still open.

Both dCache and iCache are enable. Set L1 and L2 to write-through, and L3 to None-cache-able by Configure the array "gCslR5MpuCfg," which tansplant from SDK. The BSS segment and SPI driver are placed on L3

0 Feng Pei over 3 years ago in reply to Frank Livingston

Prodigy 20 points

We use LAuterbach debuger, the GUI is Trace32，GUI can show the ECU state is "RUNING", but can not reply the "STOP/BREAK" request. Any register and memory location show ?????

0 Prasad Jondhale over 3 years ago in reply to Feng Pei

TI__Mastermind 27743 points

Hi Feng,

Can you please provide more details on test you are running when the stall happens? you mentioned CAN is open, can you please confirm if stall happens during CAN transfer?

Regards,

Prasad

0 Kowshik Gudimetla over 3 years ago in reply to Prasad Jondhale

TI__Genius 15435 points

Feng Pei

Just checking in on this thread, do you still need help on this thread? If yes can you please update on the prasad's latest comment?

0 Feng Pei over 3 years ago in reply to Prasad Jondhale

Prodigy 20 points

Hi Prasad, Sorry for late response. We've been doing a little bit of testing over the last couple of days and it's still happening.It looks like the probability of that happening has gone up since ETH MCAL was Enable. Disable Cache works fine. And the internal watchdog doesn't work when stall happens.

0 Prasad Jondhale over 3 years ago in reply to Feng Pei

TI__Mastermind 27743 points

Hi Feng,

Can you please elaborate on "Disable cache works fine"?

Does this mean full cache disable or only for Ethernet driver?

Regards,

Prasad

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AM2732: Processor Stall during test And the target did not respond to the “break“ request which sent from debugger