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TMS570LS1114: MIBSPI dynamig switching of transfer groups

Konstanty Kuczynski1
Intellectual 310 points
Part Number: TMS570LS1114

Hello,

Currently I am working on a problem where I want to dynamically change the triggering length of received message thus also the triggering of the interrupt. Currently the transfer group is set so that an interrupt is triggered after receiving 6 x 8 bits (This forms a complete message packet).

However, since the traffic is too high or the processing of the messages takes too long, we would like to dynamically adjust the length so that 15 message packets (so 15 x 6 x 8 Bits) are expected at a known time. So also only one interrupt and not 15 should be triggered.

- How exactly can I dynamically adjust the length of an existing transfer group so that the interrupt triggers differently?

- Since you can theoretically set multiple transfer groups, is there a possibility to switch between them? All should have more or less identical configurations, with the exception of the length.

I hope someone can help me here

.

Kind regards,

Konstanty Kuczynski

  • 0
    TI__Guru**** 196596 points

    Hi Konstanty,

    Does 6x8 mean six 8-bit buffers in the transfer group? The maximum length of the TG buffer is 16-bit. The TG can support up to 128 buffers.

    Yes you can change the TG size dynamically. If you use DMA for data transfer between TG buffers and SRAM, you can use two buffers in SRAM to receive the data from MibSPI RAM. Using this way, the DMA packet destination address should be changed dynamically.

  • 0 in reply to QJ Wang
    Intellectual 310 points

    Hello,

    thank you for the quick reply,

    6x8 means exactly what you write. In one case I want to receive the message after 6 buffers are received. In other case only after 90 buffers. So would it be sufficient to just write a new length to the mibspi->TGCTRL register every time before the size changes?

    Edit: Unfortunately this does not work by just reconfiguring the TGCTRL and LTGPEND. After I increase the length, not a single interrupt comes anymore. 

  • 0 in reply to Konstanty Kuczynski1
    TI__Guru**** 196596 points

    Hi Konstanty,

    Changing LPEND and PSTART of the subsequent transfer group (TG) are not enough. You also need to change the CSHOLD setting in TXRAM register. The CSHOLD of the last buffer is disabled.