Other Parts Discussed in Thread: RM46L852, HALCOGEN
Dear Champs,
My customer successfully implemented SPI on RM46L852 with DMA enabled, but they failed on RM44L520.
Is there any difference between these two devices?
By referring below, they implemented SPI4 + DMA, but still failed.
https://git.ti.com/cgit/hercules_examples/hercules_examples/tree/Application/TMS570_SPI_DMA
they modified example code slightly to use SPI4 instead of SPI3 as below.
Could you please check and let me know what they should check further?
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#define SPI4_TX_ADDR ((uint32_t)(&(spiREG4->DAT1)) + 2)
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/* - initializing mibspi*/
spiInit();
spiREG4->PC0 = 0
| (1<<11) //SOMI[0] as functional pin
| (1<<10) //SIMO[0] as functional pin
| (1 << 9) //CLK as functional pin
| (0); //CS as GIO pin
spiREG4->PC1 = 0x01; //CS[0] as output
spiREG4->PC3 = 0x00; //CS[0]=0
/* - enabling dma module */
dmaEnable();
/* Enable Interrupt after reception of data */
//dmaEnableInterrupt(DMA_CH0, FTC); //Frame transfer complete
dmaEnableInterrupt(DMA_CH0, BTC); //Block transfer complete
dmaEnableInterrupt(DMA_CH0, HBC); //Half block transfer complete
/* - assigning dma request: channel-0 with request line - 0/15 */
/* Request line 0: SPI1 Receive */
/* Request line 1: SPI1 Transmit */
/* Request line 14: SPI3 Receive */
/* Request line 15: SPI3 Transmit */
dmaReqAssign(DMA_CH0, 0); //SPI1 RX
dmaReqAssign(DMA_CH1, 25); //SPI3 TX
/* - configuring dma TX control packets */
dmaConfigCtrlTxPacket((unsigned int)&TX_DATA, SPI4_TX_ADDR, 1, BlockSize);
dmaSetCtrlPacket(DMA_CH1, g_dmaCTRLPKT_TX);
/* - configuring dma RX control packets */
/* dmaConfigCtrlRxPacket(uint32 sadd, uint32 dadd, uint32 dsize) */
dmaConfigCtrlRxPacket(SPI1_RX_ADDR, (unsigned int)&RX_DATA, 1, BlockSize);
dmaSetCtrlPacket(DMA_CH0, g_dmaCTRLPKT_RX);
/* - setting the dma channel to trigger on h/w request */
dmaSetChEnable(DMA_CH0, DMA_HW); //SPI1 RX, hardware triggering
dmaSetChEnable(DMA_CH1, DMA_HW); //SPI3 TX, hardware triggering
//For efficient behavior during DMA operations, the transmitter empty and receive-buffer full interrupts can be disabled
//The first TX_DMA_REQ pulse is generated when either of the following is true:
// 1. DMAREQEN (SPIINT0[16]) is set to 1 while SPIEN (SPIGCR1[24]) is already 1.
// 2. SPIEN (SPIGCR1[24]) is set to 1 while DMAREQEN (SPIINT0[16]) is already 1.
spiREG1->GCR1 = (spiREG1->GCR1 & 0xFFFFFFFFU) | (0x1 << 24); //Enable SPI
spiREG1->INT0 = (0x1 << 16); //SPI_DMAREQ; Enable DMA REQ only after setting the SPIEN bit to 1.
spiREG4->GCR1 = (spiREG4->GCR1 & 0xFFFFFFFFU) | (0x1 << 24); //Enable SPI
spiREG4->INT0 = (0x1 << 16); //SPI_DMAREQ; Enable DMA REQ only after setting the SPIEN bit to 1.
while( SPI4_BTCFlag == 0 ){ //DMA block complete interrupt
}
~~~~~~~~~~
Thanks and Best Regards,
SI.
