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TM4C1294NCPDT: System Divisor Factors for fVCO (PLL) available

Enric Puigvert
Prodigy 40 points
Part Number: TM4C1294NCPDT

Hello,

I am working in a project where we need to catch the rise edges of a pulsed signal. This signal has a ~5 to 10ns pulse width, and it is not periodic (they are randomly generated).

We are thinking in the idea to use the analog comparator integrated in the TM4C1294NCPDT MCU to detect this pulses and try to count them. As the analog comparator has its output registered, we know that with a 120MHz clock, we can't catch the signal.

But, could we set the system clock at the PLL's max frequency?
In other words, could we set the PLL's System Divisor Factor to 1 to get its 480MHz clock as the SYSCLK? Therefore, the analog comparator register could work at this high frequency and could catch the pulses. Is that possible?

Thank you very much in advance

Regards

Enric Puigvert 

IFAE Software & Control Department

  • +1
    TI__Guru**** 191486 points
    Enric Puigvert said:
    But, could we set the system clock at the PLL's max frequency?
    In other words, could we set the PLL's System Divisor Factor to 1 to get its 480MHz clock as the SYSCLK? Therefore, the analog comparator register could work at this high frequency and could catch the pulses. Is that possible?

    No, you cannot. The VCO output must be divided to produce the maximum allowable system clock frequency at 120Mhz. If the system clock is configured higher than 120Mhz then it is out of spec. The device will most likely not work and its operations cannot be guaranteed.