Hello,
I'm recently working on DMA-controlled SPI transfer on TMS470R1. The SPI is configured at 1,000 kHz bit rate, Master mode and DMA controller channel 7 (for RX) and channel 8 (for TX) are used for the transfer. SPI RX interrupt is disabled. The interrupt priorities of DMA line 1 interrupt and DMA line 0 interrupt are mapped to CIM level 3 and level 2 respectively. DMA control packet 7 is assigned to channel 7 and control packet 8 is assigned to channel 8. Both control packet interrupt are enabled. The following is the test use case that I have run on the debugger:
1. SPI and DMA is initialized
2. Start DMA transfer with 8 bytes of data
3. Wait for the DMA transfer complete interrupt and ISRs to be invoked
4. Read DMA Interrupt offset 1 and DMA Interrupt offset 0 in their ISR
5. Repeat step 2
The transfer was working fine for a several times (cycle of step 2 to 5) and it just stopped working after that. ISRs were not invoked. This problem was very consistent. When the problem occurred, the following registers were checked:
1. INTREQ2 and INTREQ3 - Not Pending
2. DMA Status Register : TC - 1 , PINT - 0 , and all IFx were 0
3. DMA interrupt offset 1 : 0 and DMA interrupt offset 0 : 0
4. DMA control packet registers: INTEN - 1 , TCOUNT - 0
When the problem occurred, I checked on the oscilloscope for SCLK. The waveform showed 8 clocks.
May I know what am I missing here to have caused this problem?
Your help will be greatly appreciated.
Thank you.
