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Original question:

RM48L952: [FAQ] HW trigger problem of CAN1 IF1 using DMA

RM48L952: [FAQ] Data transmission problem of CAN communication using DMA HW trigger

영호 안
Prodigy 160 points

Part Number: RM48L952

Hello, thank you for always answering my questions.
Today, I would like to ask again about the DMA HW Trigger that I asked about last time. In my code, I also enabled DMA Active of IF1 CMD and enabled DE1 of CAN CTL to apply HW Trigger, but DMA did not work.
I'm not sure how to utilize the HW trigger to copy the transmit data to the TX buffer.
Thank you for your time. Below is my code.

20220427_CAN2 (2).zip

  • 0
    TI__Guru**** 200256 points

    Hi,

    After the transfer between IF1 registers and Message RAM is completed, the DMA is requested. The DMA request remains active until the first read or write to one of the IF1/IF2 registers. An exception is a write to Message Number (Bits [7:0]) when DMA Active is 1.

    Due to the auto reset feature of the DMA Active bit, this bit has to be separately set for each subsequent DMA cycle.

    Can you try to set "DMA Active" bit before writing to IF1NO portion in your function uint32 canTransmit_DMA():

    canREG1->IF1NO = (uint8) canMESSAGE_BOX1; //CAN 통신으로 TX DATA 송신
    return 0;
    }

  • 0 in reply to QJ Wang
    Prodigy 160 points

    As you said, I modified the code, but the DMA didn't copy the data. Perhaps the DMA Active bit does not act as a DMA trigger to copy data from the source address to the destination address. If this problem is solved, it seems that data can be transmitted using HW Trigger, but DMA is not triggered.

  • 0 in reply to QJ Wang
    Prodigy 160 points

    20220923_DMA_HW_CAN.zip

    I will send you the CAN communication code using HW Trigger that I wrote again.

  • 0 in reply to 영호 안
    TI__Guru**** 200256 points

    Hi,

    I am running test, and will come back to you by tomorrow.

  • +1 in reply to QJ Wang
    TI__Guru**** 200256 points

    Hi,

    I realized that the IF1/IF2 are not suitable for DMA operation. Perhaps some clarification is needed in the TRM to list the limitation for using DMA with the DCAN.

    If you go to DCAN IF1DATA and IF1DATB registers description, these registers are write-protected meaning that they can only be written in privileged mode. However, the DMA is designed to always operate in user mode. Therefore, the DMA can never write to these DCAN registers. When a write happens from the DMA, the DCAN will simply ignore these writes.

    There is no advantage of using DMA to transfer data to the IF1/2 register even if these registers are writeable in the user mode. First, the payload is only 8 bytes. You could have written a store-multiple (STM) instruction to the IF1DATA/IF1DATB register fairly quickly instead of using the DMA where you need to set up the channels and wait for the the DMA to interrupt the CPU when the transfer is complete. Second, the DMA does not know when it is allowed to write to the registers. Before you can write to the IFx registers you will need to poll the busy bit to know whether a transfer between IFx and the message RAM is in progress. The DMA has no such capability. Only CPU does.