Hi Team,
VCLK is set to 70MHz. 4 SCIs are used, 3 of which are set to 115200 baud rate (actually 115131). 1 of them is set to 384000 (actually 397727).
The bit error rate of 384000 is too high. But if customer changes VCLK, the other 3 115200 will be affected. Customer would like to ask if there is another way to set a separate clock for a certain SCI? for baud rate configuration
Thanks,
Annie