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TMS570LC4357: DMA Data transfer

Suthan Sivamayam
Prodigy 180 points
Part Number: TMS570LC4357
Other Parts Discussed in Thread: HALCOGEN

Hi All,

I have been trying to use DMA data transfer between Port A and Port B( MibSPI). 

1. Tried with Shared memory ( normal inner & outer non-cachable and shared memory type) using MPU, as described in the example_mibspiDma.c (Halcogen/examples). This task was successful.

2. Tried with coreCleanDCByAddress and coreCleanInvalidateDCByAddress (without any MPU configurations).  I do see DMA interrupt notification when block transfer is completed but RXDATA is empty 

coreCleanDCByAddress((uint32_t)&TXDATA[0], D_SIZE << 1U);/* clean out the bytes */
coreCleanInvalidateDCByAddress((uint32_t)&RXDATA[0], D_SIZE << 1U);/* clean out and discard old cache data */

i. Is there any way to use DMA without MPU (normal inner & outer non-cachable and shared memory type) as described above or any other methods?

Thanks in advance

  • +1
    TI__Guru**** 197306 points

    Hi,

    The DMA allows data to be sent directly from an peripherals to the memory or from the memory to peripheral, freeing the CPU from involvement with the data transfer and improving the CPU's performance.

    But using DMA can lead to cache coherency problems If the CPU has a data cache and the data cache is enabled. The data in SRAM accessed by the DMA controller may not be updated with the correct data stored in the cache.

    There are two ways to solve this kind of problem:

    1. Disabling cache on memory region shared by the DMA and CPU, like you did in #1

    In this approach, the memory regions shared by the CPU and DMA are defined as non-cacheable using the Memory Protection Unit (MPU), while leaving the memory regions that are only accessed by the CPU as cacheable. Shared memory can be updated by the CPU and DMA simultaneously.

    2. Cleaning the cache before the DMA reads data from TXDATA

        Clean cache – writes the cache lines, which are marked as dirty, back to the main memory.

        #1. CPU write data to TXDATA[]

        #2. A cache clean operation to flush the cached TXDATA[] into the SRAM

        #3. The DMA reads from the SRAM will now be coherent.

    3. Invaliding the cache before 

        Invalidate cache – Marks the cache lines as invalid. Subsequent access forces the data to be copied from the main memory to the cache.

        #1. DMA writes data to the RXDATA[]

        #2. Invalidate the cached RXDATA[].

        #3. The CPU reads from the cache will then be coherent

  • +1 in reply to QJ Wang
    TI__Guru**** 197306 points
    Suthan Sivamayam said:

    coreCleanDCByAddress((uint32_t)&TXDATA[0], D_SIZE << 1U);/* clean out the bytes */
    coreCleanInvalidateDCByAddress((uint32_t)&RXDATA[0], D_SIZE << 1U);/* clean out and discard old cache data */

    When using the cache clean and cache invalidate by address APIs:

    addr – Must be aligned to the cache line size boundary. This means that the DMA buffer address must be aligned to the 32-byte boundary.

    dsize – Must be a multiple of the cache line size. This means that the DMA buffer size must be a multiple of 32-bytes.