RM48L952: DMA Channel Chaining Issues

Hi,

I got your query, and I am working on another urgent request, and will investigate the issue for you as soon as possible. 

Hi,

In your code, the DMA_CH0 is for transferring data from IF3x data register to buffer0 in SRAM, and DMA_CH1 is used to transfer data from IF3x data registers to buffer1 in SRAM. The DMA request for both CH0 and CH1 is generated automatically when IF3x update is complete.

In your code, CH1 is chained to CH0, and is triggered when CH0 transfer is done.

Does DMA_CH1 use two triggers?

One suggestion:

You can 64-bit for read/write data size:

g_dmaCTRLPKT_RX1.RDSIZE = ACCESS_64_BIT; //Read 크기
g_dmaCTRLPKT_RX1.WRSIZE = ACCESS_64_BIT; //Write 크기

g_dmaCTRLPKT_RX1.ELCNT = 1; //요소 수
g_dmaCTRLPKT_RX1.ELDOFFSET = 0; //목적지 요소 오프셋
g_dmaCTRLPKT_RX1.ELSOFFSET = 0; //시작 요소 오프셋
g_dmaCTRLPKT_RX1.FRDOFFSET =0 ; //목적지 프레임 오프셋
g_dmaCTRLPKT_RX1.FRSOFFSET = 0; //시작 프레임 오프셋
g_dmaCTRLPKT_RX1.PORTASGN = 4; //Port B Number

g_dmaCTRLPKT_RX1.TTYPE = FRAME_TRANSFER; //전송 타입
g_dmaCTRLPKT_RX1.ADDMODERD = ADDR_FIXED; //Read 오프셋
g_dmaCTRLPKT_RX1.ADDMODEWR = ADDR_INC1; //Write 오프셋

Hello, the code I posted above is for triggering CH1 using channel chaining. In the previous test, when CH1 was triggered by the BTC interrupt of CH0 without channel chaining, the data remaining in the last IF3 DAT was copied simultaneously with the trigger. But this is not the behavior I want, so I tried to use channel chaining. However, I thought that CH1 would be triggered after CH0 by channel chaining, but when IF3 DAT is updated, CH0 and CH1 are triggered at the same time, so it doesn't work as I want. I'm not sure if I'm using channel chaining incorrectly or if I've written the code wrong, so I don't know how to fix it, so I posted a question on the forum.

If IF3 update is complete, a DMA request is generated. If DMA channel 1 is not assigned to DMA request line #4 , the DMA transfer is not triggered.

I noticed that

dmaReqAssign(DMA_CH1, 4); was commented out in your code

So the DMA_CH1 should not be triggered by IF3x DMA request. 

I haven't got chance to test it.

I will do a test later today

Hi,

I got the same issue. The DMA CH1 and CH0 get triggered at the same time. I will perform more test to figure out what causes the problem.

Hi,

In DMA channel chaining, the chained channel is triggered according to the type of the first DMA channel.

If the first DMA channel is frame type, then, after each frame completion, it will trigger a request to the chained DMA channel. 

If the first DMA channel is block type, the chained channel will be triggered after one block transfer of the first channel is completed.

I think that using DMA channel chaining is not a solution to your problem.

You can start over DMA CH1 transfer, or you can trigger the DMA CH2 transfer in DMA BTC ISR.

void dmaGroupANotification(dmaInterrupt_t inttype, uint32 channel)
{

..

}

hi,
As stated in the article, if channel 2 is triggered by the BTC interrupt of channel 1, the remaining data of IF3 Datx is immediately copied to channel 2. I want to copy the next received data after channel 2 is triggered. Any solution?

Hi,

I want to give one suggestion, i dont have setup to test it but try below thing once 

Please don't call the dmaSetChEnable of CH1 immidiately after initializations, comment that line

Call this line in BTC interrupt of the CH0 as shown below

If we do this the CH1 will be activated only after CH-0 finishes, it's block transfer.

--

Thanks & Regards,

Jagadish.