SPISOMI setup time before CLK

Hi Jean Ricard,

Not sure what spec you're referring to. The technical reference manual (SPNU489A) describes the configuration of SPI delays in section 14.9.19. Is this what you're after?

Regards, Tony

Hi Tony,

I'm talking about SPNS141E as this document has the electrical specs. I want to know the minimum setup time

needed on the SPI interface (CLK) to guarantee the SOMI pin will be sampled correctly.

Regards,

Hi,

The terminal functions table specifies the output buffer drive strength for each terminal. You can see that the SPIx CLK, SIMO and SOMI outputs use the 4mA drive-strength buffer.

The rise and fall times for the 4mA output buffer versus the capacitive load seen are specified in Section 7.6 Output Timings.

-Sunil

Sunil,

The setup time is related to the input, just to be clear, if I have a rising edge at CLK pin, how long before the data at SOMI pin must be stable.

Thanks,

Yes, that is correct - when the SPIx on the TMS570 micro is in master mode, the SOMI (slave out master in) is an input signal. If the clock polarity is 0, then the master transmits (on SIMO) with respect to the rising edge of SPICLK and expects to sample the input (SOMI) on the falling edge of SPICLK.

The slave must drive its output (SOMI) such that it meets the minimum setup time for SOMI required by the master.

-Sunil

Sunil,

what is the time needed, that is what I need to know.

The setup time at the pin seems to be 4 ns if I look at the slave interface, that is the data I need.