Part Number: AM2634-Q1
I have a system that is running numerous ISRs from PWMs, GPI, Timers and ECAPs. I would like to prioritize my PWM and external GPI ISRs over all other ISRs.
How did setup and process the ISR handlers that will check if the PWM or GPI ISR flags are not set before handling the current "lower" priority ISR?
Thanks in advance.
Hi Tim
In R5 we have VIM for Interrupt management. Each interrupt has its own 4-bit programmable priority --> R5FSS_VIM_PRI_INT_j register.
The VIM supports the interruption of the currently active interrupt by one with a higher priority.
VIM priority scheme: 00 = Highest Priority - 15 = Lowest Priority.
1. When an interrupt goes from pending to active, then the interrupt is loaded into the corresponding active register, and all interrupts of an equal or lesser priority are masked.
2. If prior to this interrupt being cleared, another interrupt of higher priority arrives, then the IRQn is asserted and that interrupt made pending as normal.
3. If the CPU switches this interrupt to active, then the currently active interrupt is pushed onto a stack. When an interrupt is cleared by reading the R5FSS_VIM_FIQVEC / R5FSS_VIM_IRQVEC register, if there are any interrupts on the stack, the first entry is popped off and put back into the R5FSS_VIM_ACTFIQ / R5FSS_VIM_ACTIRQ register, so that software retains original context and continues previous operation.
For more detailed information, please refer to 10.2.1.8 VIM Interrupt Handling section of the TRM.
The priority of the interrupt can be set while constructing the interrupt.
