TMS570LS3137: Is there a routine for the ECC function of the TMS570LS3137 chip?

All accesses to the on-chip flash memory and SRAM are protected by dedicated Single-Bit Error Correction Double-Bit Error Detection (SECDED) logic. There is an 8-bit ECC for every 64 bits of data. The ECC for the flash memory contents needs to be calculated by an external tool such as CCS, Uniflash, or bootloader which uses Flash APIs to program the application image.

The SECDED logic inside the Cortex-R4F CPU is not enabled by default and must be enabled by the application. The driver generated via HALCoGen includes APIs for enabling the ECC:

/* Disable RAM ECC before doing PBIST for Main RAM */
_coreDisableRamEcc_();

/* Enable ECC checking for TCRAM accesses.
* This function enables the CPU's ECC logic for accesses to B0TCM and B1TCM.
*/
_coreEnableRamEcc_();

/* Enable CPU ECC checking for ATCM (flash accesses) */
_coreEnableFlashEcc_();

When the CPU detects an ECC single-, or double-bit error on a read from the flash memory or SRAM memory, it signals this on a dedicated “Event” bus, and the ECC error is reported to ESM. This event bus signaling is also not enabled by default and must be enabled by the application:

/* Enable CPU Event Export */
/* This allows the CPU to signal any single-bit or double-bit errors detected
* by its ECC logic for accesses to program flash or data RAM.
*/
_coreEnableEventBusExport_();

To test the CPU ECC mechanism for RAM accesses, please refer to the SRAM selftest function in Safety Diagnostic Library:

boolean SL_SelfTest_SRAM(SL_SelfTestType testType, boolean bMode, SL_SelfTest_Result* sram_stResult)

The function causes deliberate single-bit and double-bit errors in TCRAM accesses by corrupting 1 or 2 bits in the ECC. Reading from the TCRAM location with a 2-bit error in the ECC causes a data abort exception. 

/* Run 1Bit ECC test on TCM RAM */
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_1BIT, TRUE, &failInfoTCMRAM);

/* Run 2Bit ECC test on TCM RAM */
retVal = SL_SelfTest_SRAM(SRAM_ECC_ERROR_FORCING_2BIT, TRUE, &failInfoTCMRAM);

Hi,

Thanks for your great help!

1.For _coreEnableEventBusExport_();

I would like to ask again if this event bus is enabled, if ECC single-error or double-error occurs, which interrupt function or some error event function does it enter?

2.I tried to enable flash ECC checking in your way, and I deliberately made single and double errors, but as soon as I ran flash read, the program ran and jumped into the lower level of assembly code: 

Here at flashErrorreal , why, how to fix this problem so the program runs?

flashErrorReal
        b       flashErrorReal      ;branch here forever as continuing operation is not recommended

esmsr3          .word   0xFFFFF520
ramctrl         .word   0xFFFFF800
ram2ctrl        .word   0xFFFFF900
ram1errstat     .word   0xFFFFF810
ram2errstat     .word   0xFFFFF910
flashbase       .word   0xFFF87000

    .endasmfunc

Thanks and regards,

Ben

Hi Ben,

Ben Qin said:

1.For _coreEnableEventBusExport_();

If the event bus export is enabled, the ECC error will also be reported to ESM module. If the interrupt of ESM channel is enabled, yes, it will enter the ESM interrupt routine. The default interrupt handler is low priority ESM interrupt which is disabled by default. 

The interrupt of ESM group2 channels is always enabled, and the high priority ESM interrupt handler (ESM FIQ) is used:

Ben Qin said:

2.I tried to enable flash ECC checking in your way, and I deliberately made single and double errors, but as soon as I ran flash read, the program ran and jumped into the lower level of assembly code: 

It is expected. The double flash ECC error will generate data abort. So data abort interrupt handler is called. If the ECC is generated by flash or SRAM ECC selftest, the error flags will be cleared, then code execution jumps back to selftest function.

If the ECC error is not generated by self-test, it will call flashErrorreal. Data abort is a severe error, you have to stop code execution to debug your code.