TMS570LC4357: Mapping CPU Interconnect Subsystem Safety Features and Diagnostics to ESM Groups and Channels

Hello,

I am using the TMS570LC4357 and I am trying to reconcile the Safety Features and Diagnostics listed in the "Safety Manual for TMS570LC4x Hercules ARM Safety MCUs" (SPNU540A) with the ESM Channels described in the datasheet for the TMS570LC4357 Hercules (SPNS195C).


The "Safety Manual for TMS570LC4x Hercules ARM Safety MCUs" (SPNU540A) describes the following four safety features and diagnostics.
    CPU Interconnect Subsystem MEM9 CPU Interconnect Hardware Checker
    CPU Interconnect Subsystem MEM10 Timeout Monitoring on Bus Transactions
    CPU Interconnect Subsystem MEM11 Transaction ECC (Date Lines)    
    CPU Interconnect Subsystem MEM12 Transaction Parity (Address and Control Lines)

Table 4 states that the action on detected fault for all of these safety features and diagnostics is "ESM Error".


In Table 6-45 of the datasheet for the TMS570LC4357 Hercules (SPNS195C) there are three ESM Error Sources for the CPU Interconnect Subsystem :
    CPU Interconnect Subsystem - Global error (1.52)
    CPU Interconnect Subsystem - Global Parity Error (1.53)
    CPU Interconnect Subsystem - Diagnostic Error (3.12)
    
Presumably, CPU Interconnect Subsystem MEM12 Transaction Parity (Address and Control Lines) corresponds to CPU Interconnect Subsystem - Global Parity Error (1.53). Is this correct?

How do the other three CPU Interconnect Subsystem diagnostics (MEM9, MEM10 & MEM11) map to the other two ESM Error Sources (1.52 and 3.12)?


Thank you.