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AM2634: Is the system clock frequency fixed? How do I configure the PLL to generate clocks for each peripheral?

Ben Qin
Intellectual 2690 points
Part Number: AM2634
Other Parts Discussed in Thread: SYSCONFIG

Hi,team

Here's the issue form the customer may need your help:

Using the ePWM module's routine to debug on the CC board, measure the PWM frequency and assume that the ePWM clock is 200 MHz, but the WUCPUCLK configured in sysconfig is 25 MHz, how does it multiply? It is seen in the chip manual that the clock for the AM263 is a few fixed frequency options such as 25MHz, 200MHz, 400MHz, etc., which is very different from the C2000 configuration PLL generation SYSCLK. SYSCLK is not described in the manual.

Could you help check this case?Thanks.

Best Regards,

Ben

  • 0
    TI__Intellectual 2690 points

    Hi Team,

    May I know is there any update for this question?

    Thanks,

    Ben

  • 0 in reply to Ben Qin
    TI__Expert 7600 points

    Hi Ben, 

    WUCPUCLK does not multiply to 200MHz, but rather the device needs the R5 to use a known-stable 25MHz clock and then the R5SS0 clock gets reconfigured to operate at 400MHz by the gels. 

    In AM263x, SYSCLK operates on an achievable ratio with the R5SS clock, which is either 1:1 operating SYSCLK at 400MHz, or a 2:1 operating SYSCLK at 200MHz.

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    TI__Intellectual 2690 points

    Hi Daniel,

    Thanks for your great help!

    So can the 263 system clock be configured? Like 300 megahertz or 150 megahertz. Also, how can the system clock be divided down to peripherals, such as the PWM and ADC clocks, be adjusted?

    Best Regards,

    Ben

  • +1 in reply to Ben Qin
    TI__Expert 7600 points

    Hi Ben,

    Ben Qin said:
    So can the 263 system clock be configured?

    Yes it can, I want to make a correction on my previous reply: 

    Daniel Bermudez said:
    In AM263x, SYSCLK operates on an achievable ratio with the R5SS clock, which is either 1:1 operating SYSCLK at 400MHz, or a 2:1 operating SYSCLK at 200MHz.

    What I meant so say was the following:

    "In AM263x, SYSCLK operates on an achievable ratio with the R5SS clock, which is either 1:1 operating R5SS at 400MHz, or a 2:1 operating R5SS at 200MHz". 

    I apologize for the confusion.

    Going back to your question, system clock can be adjusted by modifying the value in the SYS_CLK_DIV_VAL.CLKDIV register. This process is more detailed in section 6.4.1.2.3.2.1 Sequence for Programming SYS and R5 Clocks of the TRM:

    Some peripherals contain additional configuration and divider blocks at their IP level block that would allow you to modify the output clock further even after the functional clock feeds into the IP, for example such is the case with peripherals like SPI and UART that are external communication protocols that require an output clock for correct functionality. 

    So yes, the system clock can be divided down to peripherals and some of them contain additional divider blocks, for this reason I'd suggest going over the TRM chapter of the IPs of interest for additional information on exactly how much configurability you have available at a time.

    Best,

    Daniel 

    Link to TRM: AM263x SitaraTm Microcontroller Technical Reference Manual (Rev. B) (ti.com)

    Link to Register Addendum: AM263x Sitara Processors Technical Reference Manual Register Addendum (Rev. B) (ti.com)