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AM2634: Is it possible to handle same pins in different cores dynamically in dual core mode?

Sharmili Narayanamurthy
Prodigy 110 points

Part Number: AM2634

Hi,

I had tried to verify whether same Hardware pins can be made use by different cores in dual core mode.

For example: Will it be possible to toggle a same GPIO pin in different cores? 

I tried the same & ended up seeing only one core's (the last core that was flashed) output.

Thanks in advance.

Regards,

SN

  • 0
    TI__Mastermind 30108 points

    Hi SN,

    I'm looking into this and will get back with you shortly.

    Regards,
    Frank

  • +1 in reply to Frank Livingston
    TI__Mastermind 26195 points

    Hi Sharmili,

    The device does not support hardware semaphore but you can use IPC Notify to create a Semaphore to detect if the resource (GPIO) being used here is free or not. I suggest you to have this implementation while using multicore communications.

    Best Regards,
    Aakash

  • +1
    TI__Mastermind 30108 points

    Hi SN,

    Adding to this regarding GPIO:

    Please see the AM263x TRM (www.ti.com/.../spruj17), Section 13.1.1.3.1 GPIO Integration:

    • "Note: There is a designated GPIO module per R5FSS core. Each R5FSS core has access to all GPI signals. The GPO signals can be assigned to a specific R5FSS core by configuring the MSS_IOMUX.PAD_CFG_REG.GPIO_SEL[17:16] of the associated IOMUX Pad Configuration register."
    • Figure 13-2. GPIO Mux Diagram

    The GPIO_SEL configuration can be changed dynamically using the Pinmux_config() function, e.g.:

    Pinmux_PerCfg_t pinmuxCfg[2];

...

/* Assign GPIO to R5F0_1 */
pinmuxCfg[0].offset = PIN_QSPI_CSN1;
pinmuxCfg[0].settings = ( PIN_MODE(7) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_QUAL_SYNC | PIN_GPIO_R5SS0_1 );
pinmuxCfg[1].offset = PINMUX_END;
Pinmux_config (pinmuxCfg, PINMUX_DOMAIN_ID_MAIN);

/* Assign GPIO to R5F0_0 */
pinmuxCfg[0].offset = PIN_QSPI_CSN1;
pinmuxCfg[0].settings = ( PIN_MODE(7) | PIN_PULL_DISABLE | PIN_SLEW_RATE_LOW | PIN_QUAL_SYNC | PIN_GPIO_R5SS0_0 );
pinmuxCfg[1].offset = PINMUX_END;
Pinmux_config (pinmuxCfg, PINMUX_DOMAIN_ID_MAIN);

    Ownership between cores would need to be arbitrated in SW as mentioned by Aakash.

    Regards,
    Frank