TMS570LS3137: Clarification on EMIF_CLK max frequency

Federico Gobetti

Part Number: TMS570LS3137
Other Parts Discussed in Thread: TMDS570LS31HDK

Hello,

I write to have a confirmation on the spec of the signal EMIF_CLK:

The example at "17.2.5.6.1 Determining the Appropriate Value for the RR Field" and the whole "17.4 Example Configuration" chapters of the TRM set f(emif_clk) to 100MHz.

In the TMS570LS3137 datasheet, the "Table 6-27. EMIF Asynchronous Memory Timing Requirements" sets the minimum EMIF clock period to 11ns (i.e. up to 90.9MHz), but in the "Table 6-30. EMIF Synchronous Memory Switching Characteristics" the minimum EMIF_CLK cycle time is 20ns (i.e. a max frequency of 50MHz).

Can you please clarify which is the max EMIF_CLK to use for both SDRAM and async devices?

Thanks in advance,
Federico.

over 2 years ago

0 jagadish gundavarapu over 2 years ago

TI__Guru 63035 points

Hi Federico,

Sorry about the confusion, but the Datasheet AC characteristics have to be used. Treat the TRM chapter as an example calculation but you've got to plug in the new numbers from the datasheet.

The max EMIF_CLK for the SDRAM interface in TMS570LS3137 is 50MHz.

The max EMIF_CLK for the Async device in TMS570LS3137 is 90MHz.

Thanks & Regards,
Jagadish.

0 Federico Gobetti over 2 years ago in reply to jagadish gundavarapu

Prodigy 80 points

Hi Jagadish,

thank you for your answer, but can you please explain why the async device can run up to 90MHz and the SDRAM cannot? Which peculiar aspects may fail at 90MHz?
I want to connect both an SDRAM and a couple of async devices to the EMIF interface but slowing the frequency down for the SDRAM may be a bottleneck for the async devices that can run faster!

I did some experimentations with the IS42S16400J SDRAM on the TMDS570LS31HDK dev kit and it seems to work fine at 90MHz.
In which condition may face problems?

0 jagadish gundavarapu over 2 years ago in reply to Federico Gobetti

TI__Guru 63035 points

Federico Gobetti said:
async device can run up to 90MHz and the SDRAM cannot? Which peculiar aspects may fail at 90MHz?

The EMIF clock for sync and Async are specified in datasheet will be applicable for all over operating conditions of the device.

Those value are for worst case, for example high temperature.

Federico Gobetti said:
In which condition may face problems?

We can't tell exactly on which condition the problem occurs, but for extreme operating conditions like temperature and voltage you might face the problems.

--
Thanks & Regards,
Jagadish.

0 Federico Gobetti over 2 years ago in reply to jagadish gundavarapu

Prodigy 80 points

We recently conducted some climatic tests on our hardware, equipped with the same SDRAM of the dev kit and running EMIF_CLK at 90MHz (half the 180MHz HCLK setting), and we didn't notice any fails.

jagadish gundavarapu said:
We can't tell exactly on which condition the problem occurs, but for extreme operating conditions like temperature and voltage you might face the problems.

What kind of fail should we expect?

In this old thread
https://e2e.ti.com/support/microcontrollers/arm-based-microcontrollers-group/arm-based-microcontrollers/f/arm-based-microcontrollers-forum/260952/trouble-with-tms570ls31-hdk-sdram

Anthony F. Seely said:
"1) The device can't run with EMIF at 90MHz, the maximum is 66.67MHz according to the datasheet (15ns emif clock period)".

I guess this spec was written in an older datasheet revision (document SPNS162A) which was subsequently corrected to 20ns per period. Are there any data, graphs, derating curves or anything else supporting this correction?

45MHz SDRAM on a 180MHz processor may cause a relevant performance problem to our project, becoming worse because the async devices are stuck to the same frequency too.
Any additional information would be appreciated since we have to review our project in order to manage this downgrade.

0 jagadish gundavarapu over 2 years ago in reply to Federico Gobetti

TI__Guru 63035 points

Hi Federico,

Let me discuss with internal team and come back on this.

--
Thanks & Regards,
Jagadish.

0 jagadish gundavarapu over 2 years ago in reply to jagadish gundavarapu

TI__Guru 63035 points

Hi Federico,

The internal team confirmed the same, i mean the maximum SDRAM EMIF_CLK supported in this device is 50MHz only.

Federico Gobetti said:
What kind of fail should we expect?

The data may not be written correctly at maximum operating temperature (i.e.,125°C).

Thanks & Regards,
Jagadish.

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TMS570LS3137: Clarification on EMIF_CLK max frequency