AM2732: Low power questions

Paul,

I have the answers to a few of your questions now, I will have answers for the rest of them throughout the week.

Q4: In the DS (page 23) both pad V17 and pad W17 can pinmux out RCSS_MCASPC_DAT2. At the same time RCSS_MCASPC_DAT3 is not available on any pad. Is this a typo?

• RCSS_MCASP_DAT3 is available on pad V17 (pinmux mode 4).  This is a typo in the datasheet, and will be corrected.

Q5: the LVCMOS Vih (input voltage high for LVCMOS pins) parameter for 1.8V mode is specified as 1.71V, which is the same as the minimum VIOIN value for 1.8V mode. This is practically impossible with any driving circuit if VIOIN is close to its minimum value and gives no room for noise margin. What is the real Vih for 1.8V LVCMOS inputs?

• The real Vih is 1.71V to guarantee a "high" reading on the LVCMOS.  The noise margin is to be measured from 1.8V, NOT 1.71V.  We suggest running this supply from 1.8V, where the allowable noise margin is the difference between 1.8V and 1.71V.  

Regards,

Brennan

Q2: The VPP power input voltage is specified to be 1.7V, but the current usage is not. The EVM board has a 1A LDO on this input, which seems rather strange. Do you have any specification for the current usage on this pin?

• The maximum current on VPP is 100mA.

Brennan,

Q4: thank you for the quick reply, I corrected our pinmux table for pad V17.

Q5: (Vih in 1.8V supply operation), can you please confirm with the design team that the real Vih is 1.71V? The JEDEC LVCMOS specification for 1.8 V supply is given as 65% of the Vio_supply, not a hard value. And it is almost impossible to find any semiconductor that is specified to have Voh>=1.71V, even if the supply is the nominal 1.8V. For almost all chips Voh=Vio_supply-0.45V, as specified in the JEDEC standard. If you have this tight tolerance on the GPIO inputs, we are then forced to use 3.3V GPIO and level translate to 1.8V LVCMOS with a translator IC that upholds this tight tolerance (if we can find any).

Looking at the datasheet Vil is also unrealistic for the 3.3V mode, being higher than the Vih for the 3.3V mode... I didn't notice it before because we want to use the 1.8V mode. Can you please clarify these values?

Paul, 

Q3: there is no timing specification for the McASP peripherals (neither in the DS nor in the TRM). Do you have any specs especially regarding the maximum bit clock rate?

• Please refer to the following table for the MCASP timing requirements:

I will gather more details and clarification on Q5 for you.

Q5:  Per the design team, all LVCMOS IO parameters (VIL, VIH, VOL, VOH, etc) in both 1.8V mode and 3.3V mode are JEDEC compliant.

The minimum supply voltage in 1.8V mode is 1.71V.

Brennan,

Thanks for these answers, they were most helpful! I assume you have not received any feedback on Q1.

I have a new question, though:

Q6: in the datasheet p. 50 Table 7-11 the DC-VIL for the CMOS level input clock is defined as 20mV. Can you confirm this? It seems as unrealistic as the other VIL specifications.

Paul,

I am still working on getting you an answer for Q1.

Q6: in the datasheet p. 50 Table 7-11 the DC-VIL for the CMOS level input clock is defined as 20mV. Can you confirm this? It seems as unrealistic as the other VIL specifications.

• This is an error, the DC-VIL value should be 0.2V
• Please note that the DC-VIH values are also inaccurate in the datasheet.  The correct values for DC-VIH are:
  • Min: 1.6V
  • Max: 1.95V 

Thank you for the quick response! I'll wait for the answer on Q1, possibly creating our test board with both possibilities.