TMS570LC4357: Configuration in halcogen tool in of PBIST Controller to Run Self-Test on ALL RAM Groups

Hi Srinivasa,

You can install SafeTI Diagnostic library in below path

SAFETI_DIAG_LIB Driver or library | TI.com

In this library you can find a file called "sl_selftest.c", this file consists of different diagnostic function routines.

In this file the function "SL_SelfTest_PBIST" performs the PBIST, here by-passing different RAM group addresses you can perform different RAM group PBIST tests.

OR

You can refer below thread and utilize the code shared by QJ here:

(4) RM57L843: Enabling the PBIST test for March13N Single-Port algorithm - Arm-based microcontrollers forum - Arm-based microcontrollers - TI E2E support forums

--
Thanks & Regards,
Jagadish.

void PBIST_SelfTest(uint32 raminfoH, uint32 raminfoL, uint32 algomask)
{
volatile uint32 i = 0U;

/* PBIST ROM clock frequency = HCLK frequency /2 */
/* Disable memory self controller */
systemREG1->MSTGCR = 0x00000105U;

/* Disable Memory Initialization controller */
systemREG1->MINITGCR = 0x5U;

/* Enable PBIST controller */
systemREG1->MSINENA = 0x1U;

/* Enable memory self controller */
systemREG1->MSTGCR = 0x0000010AU;

/* wait for 64 VBUS clock cycles at least, based on GCLK to VCLK ratio */
for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }

/* USER CODE BEGIN (18) */
/* USER CODE END */

/* Enable PBIST clocks and ROM clock */
pbistREG->PACT = 0x1U;

/* Select all algorithms to be tested */
pbistREG->ALGO = algomask;

/* Select RAM groups */
pbistREG->RINFOL = raminfoL;

/* Select all RAM groups */
pbistREG->RINFOU = raminfoH;

/* ROM contents will not override RINFOx settings */
pbistREG->OVER = 0x0U;

/* Algorithm code is loaded from ROM */
pbistREG->ROM = 0x3U;

/* Start PBIST */
pbistREG->DLR = 0x14U;

}

void pbistStop(void)
{
/* USER CODE BEGIN (20) */
/* USER CODE END */
/* disable pbist clocks and ROM clock */
pbistREG->PACT = 0x0U;
systemREG1->MSTGCR &= 0xFFFFFFF0U;
systemREG1->MSTGCR |= 0x5U;
/* USER CODE BEGIN (21) */
/* USER CODE END */
}

boolean pbistIsTestCompleted(void)
{
/* USER CODE BEGIN (22) */
/* USER CODE END */

return ((systemREG1->MSTCGSTAT & 0x1U) != 0U);
/* USER CODE BEGIN (23) */
/* USER CODE END */
}

boolean pbistIsTestPassed(void)
{
/* USER CODE BEGIN (24) */
/* USER CODE END */
boolean status;

if ((pbistREG->FSRF0 == 0U) && (pbistREG->FSRF0 == 0U))
{
status = TRUE;
}
else
{
status = FALSE;
}

QJ  code ,shall i use for this code PBIST for doing self test.

#define PBISTALGO_MARCH13N_2PORT 0x00000134

#define PBIST_RAMGROUP_10_MIBSPI1 0x0000000200u /**< */
#define PBIST_RAMGROUP_11_MIBSPI2 0x0000000400u /**< */
#define PBIST_RAMGROUP_12_MIBSPI3 0x0000000800u /**< */

int main(void)
{
int retval;
/* USER CODE BEGIN (3) */
/* USER CODE END */

PBIST_SelfTest(PBIST_RAMGROUP_10_MIBSPI1,PBISTALGO_MARCH13N_2PORT);
while (TRUE != pbistIsTestCompleted());
retval = pbistIsTestPassed();
if(retval == 1)
{
pbistStop();
}
}

void PBIST_SelfTest(uint32 raminfoL, uint32 algomask)
{
volatile uint32 i = 0U;

/* PBIST ROM clock frequency = HCLK frequency /2 */
/* Disable memory self controller */
systemREG1->MSTGCR = 0x00000205U;

/* Disable Memory Initialization controller */
systemREG1->MINITGCR = 0x5U;

/* Enable PBIST controller */
systemREG1->MSINENA = 0x1U;

/* Enable memory self controller */
systemREG1->MSTGCR = 0x0000020AU;

/* wait for 64 VBUS clock cycles at least, based on GCLK to VCLK ratio */
for (i=0U; i<(32U + (32U * 1U)); i++){ /* Wait */ }

/* USER CODE BEGIN (18) */
/* USER CODE END */

/* Enable PBIST clocks and ROM clock */
pbistREG->PACT = 0x1U;

/* Select all algorithms to be tested */
pbistREG->ALGO = algomask;

/* Select RAM groups */
pbistREG->RINFOL = raminfoL;

/* Select all RAM groups */
pbistREG->RINFOU = 0x00000000;

/* ROM contents will not override RINFOx settings */
pbistREG->OVER = 0x0U;

/* Algorithm code is loaded from ROM */
pbistREG->ROM = 0x3U;

/* Start PBIST */
pbistREG->DLR = 0x14U;

}

void pbistStop(void)
{
/* USER CODE BEGIN (20) */
/* USER CODE END */
/* disable pbist clocks and ROM clock */
pbistREG->PACT = 0x0U;
systemREG1->MSTGCR &= 0xFFFFFFF0U;
systemREG1->MSTGCR |= 0x5U;
/* USER CODE BEGIN (21) */
/* USER CODE END */
}

int pbistIsTestCompleted(void)
{
/* USER CODE BEGIN (22) */
/* USER CODE END */

return ((systemREG1->MSTCGSTAT & 0x1U) != 0U);
/* USER CODE BEGIN (23) */
/* USER CODE END */
}

int pbistIsTestPassed(void)
{
/* USER CODE BEGIN (24) */
/* USER CODE END */
int status;

if ((pbistREG->FSRF0 == 0U) && (pbistREG->FSRF0 == 0U))
{

status = TRUE;
}
else
{

status = FALSE;
}
/* USER CODE BEGIN (4) */
/* USER CODE END */
}

my evalutions  board is TMS570LC43X

my PBIST code is not working may u please help me regarding this.

thanks and regards

srinivasa k

i have taken ram group select  same as yours ,but when iam sending the code i made mistake, thank you sir got answer.

thanks and regards

srinivasa k