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AM62X02 A53 Core Function safety question

Xuliang Liang
Prodigy 10 points
Function safety question!
For the SOC AM6201, Ordering Number is :AM62X02
AS I see from the safety manual(AM62Q Safety Manual draft v0.2.pdf)," In the 5.1 ARM Cortex-A53 Subsystem.  "A53 can use for safety-related processing , but need to using the suggested diagnostics as below."
My question is below:
1. Does the A53 core have functional safety certification from ARM?
2. It means that , A53 using the diagnostics, so it can compliant ASIL  and which Level (A B C D)?
3. The diagnostics has bee integrate into the library code, directly invoking it ?
4. Does the TI AM62X02 Library code intergate STL(Software Test library) for used? see below information.
Any questons, pelase contact me
  • +1
    TI__Expert 6880 points

    Hello,

    A53 does not come with safety certification from ARM. In order to use A53 for a safety function in an ASIL-B system, the diagnostics listed in the safety manual should be implemented by the systems integrator. We are targeting ASIL-B with AM62x device.  ARM STL is not integrated into the TI provided libraries and should be sourced directly from ARM. Please refer to the diags provided in the safety manual to get an idea on the type of implementation will be needed for safety on the A53 cores.

    Regards,
    Neelima

  • +1 in reply to Neelima Muralidharan
    Prodigy 10 points

    In the Arm safety IP feedback, A53 is compliant Safety here is the link, Why you said A53 safety certification does not come from Arm?

    In Arm Safety IP list, A53 core is meet safety, why in the "AM62Q Safety Manual draft v0.2.pdf" is not use for safety ? 

    If A53 need safety certification/compliant , using Arm Software Test Library or TI own diagnostic safety mechanism can meet the safety compliant?

  • +1 in reply to Xuliang Liang
    TI__Expert 6880 points

    Hello Xuliang,

    We integrate the ARM IP into our design and provide safety diagnostic mechanisms for A53. The ARM RTL supports ECC and parity on memories. TI provided safety mechanisms listed in the safety manual are sufficient to achieve ASIL-B on the A53 IP. Transient and Permanent faults in memory are covered by ECC and Parity. For CPU execution transient or permanent faults, one of the diagnostics CPU1B/CPU1C/CPU1D or CPU1E shall be implemented by the system integrator. We do not mandate the usage of ARM Software Test Libraries as the recommended mechanisms in the manual will be sufficient to meet the required integrity level. 

    Regards,
    Neelima