AM2634: Question on CORE PLL clock setting

Hi team,

Here's some question from customer that may need your help:

1. Please confirm whether the part marked in yellow in the figure below should be DPLL_PER_HSDIV0_CLKOUT1. In TRM DPLL_PER_HSDIV0_CLKOUT1 is 192MHz.

2. Is the frequency value on the right(DPLL_PER_HSDIV0_CLKOUT1 and so on) in the figure above fixed? Can it be modified?

3. Can the frequency multiplication coefficient of 25MHz to 2000MHz CORE PLL be modified? Thanks!

Best, 

Julia