Part Number: AM2634
Dear E2E team.
I testing qspi bootloader on a AM2634 and EVM cc type.
I made multicore image and uploaded to external flash.
bootloader has recognized magic word and assigned core number correctly but bootloader was hang at bottom of below function.
void SOC_rcmsetR5SysClock(uint32_t cr5FreqHz, uint32_t sysClkFreqHz, uint32_t cpuId)
{
CSL_top_rcmRegs *ptrTopRCMRegs;
uint32_t Finp, clockStatus = 0U;
uint32_t moduleClkDivVal;
ptrTopRCMRegs = SOC_rcmGetBaseAddressTOPRCM ();
Finp = SOC_rcmGetCR5SysclkInFrequency();
/* 1. Program SYS CLK GCD register with the value of 0x111 in-order to switch to a new desired frequency, SYS_CLK_DIV_VAL.CLKDIV = 0x111
2. Poll for the CURRDIVR field of corresponding status register to reflect its new frequency change, SYS_CLK_STATUS. CURRDIVIDER = 0x1
*/
moduleClkDivVal = SOC_rcmGetModuleClkDivVal(Finp, sysClkFreqHz);
ptrTopRCMRegs->SYS_CLK_DIV_VAL = SOC_rcmInsert16 (ptrTopRCMRegs->SYS_CLK_DIV_VAL, 11U, 0U, SOC_rcmGetModuleClkDivRegVal(moduleClkDivVal));
/*
3. If the R5 clock frequency needs to be same as SYS clock frequency, then program the R5SS0_CLK_DIV_SEL.CLKDIVSEL = 0x7 (or / and) R5SS1_CLK_DIV_SEL.CLKDIVSEL = 0x7 register(s) as required or else leave with default value of 0x0 without any programming
*/
/* Divide by 1 to get the R5 Core Clock */
moduleClkDivVal = SOC_rcmGetModuleClkDivVal(Finp, cr5FreqHz);
if ((cpuId == CSL_CORE_ID_R5FSS0_0) || (cpuId == CSL_CORE_ID_R5FSS0_1))
{
ptrTopRCMRegs->R5SS0_CLK_DIV_SEL = SOC_rcmInsert16 (ptrTopRCMRegs->R5SS0_CLK_DIV_SEL, 11U, 0U, SOC_rcmGetModuleClkDivRegVal(moduleClkDivVal));
}
else if ((cpuId == CSL_CORE_ID_R5FSS1_0) || (cpuId == CSL_CORE_ID_R5FSS1_1))
{
ptrTopRCMRegs->R5SS1_CLK_DIV_SEL = SOC_rcmInsert16 (ptrTopRCMRegs->R5SS1_CLK_DIV_SEL, 11U, 0U, SOC_rcmGetModuleClkDivRegVal(moduleClkDivVal));
}
else
{
/* Nothing to be done here */
}
/* 4. After the divider configuration, update the R5SS GCM register with the value of 0x222 to select the PLL_CORE_CLOCKOUT0 as its source, R5SS_CLK_SRC_SEL.CLKSRCSEL= 0x222
*/
/* Select CLKOUT0 as clock for R5 Core */
ptrTopRCMRegs->R5SS_CLK_SRC_SEL = SOC_rcmInsert16 (ptrTopRCMRegs->R5SS_CLK_SRC_SEL, 11U, 0U, gR5SysClkSrcValMap[SOC_RcmPeripheralClockSource_DPLL_CORE_HSDIV0_CLKOUT0]);
/* 5. Poll for the CLKINUSE field of corresponding status register to reflect its new frequency change, R5SS_CLK_STATUS.CLKINUSE = 0x04 */
do
{
clockStatus = SOC_rcmExtract8 (ptrTopRCMRegs->R5SS_CLK_STATUS, 7U, 0U);
}while(clockStatus != 0x4U);
}
The code has changed R5SS0_CLK_DIV_SEL register but never changed.
I assume that reason is locking mechanism.
other code on the soc_rcm.c has lock and unlock routine(SOC_controlModuleLockMMR, SOC_controlModuleUnlockMMR).
SOC_rcmsetR5SysClock function also need unlock routine, is right?
