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AM2431: XIP memory map write (MRAM)

tom
Prodigy 210 points
Part Number: AM2431

Hi,

I have a questions regarding writes in OSPI XIP mode. (not running code from the device, just data)

When using OSPI boatloader it is possible to configure OSPI device in XIP mode for memory mapped reads.

I understand that memory mapped writes are not possible in SPI Flash due to flash storage limitations.(erase,page write)

SPI MRAM/FRAM do not have these write limitations.

Is it possible to use memory map to do writes in that case?

best regards,

Tom

  • 0
    TI__Mastermind 26145 points

    Hi ,

    I could not understand the question. 

    tom said:
    I understand that memory mapped writes are not possible in SPI Flash due to flash storage limitations.(erase,page write)

    This is correct. Even if the memory is XIP, you need to use FlashAPIs to erase/program and this won't be as similar to writing to a RAM.

    But if you are not executing your code from XIP, it is just another device with external flash.

    tom said:
    SPI MRAM/FRAM do not have these write limitations.

    We do not have MRAM/FRAM capabilities in AM243x. For more details regarding the same, please reach out to Sales and Marketing Team of TI.

    Best Regards,
    Aakash

  • 0 in reply to Aakash Kedia
    Prodigy 210 points

    Everspin has QSPI MRAM with XIP support. (MR10Q010)

    Since it is random access memory I was wondering wether you could write to the device by writing to 0x60000000 pointer. 

  • 0 in reply to tom
    TI__Mastermind 26145 points

    Hi ,

    We have requested the subject matter expert to comment on this. He is unavailable at this point, so please expect some delay in response.

    Best Regards,
    Aakash

  • 0 in reply to Aakash Kedia
    TI__Expert 7630 points

    Hi Tom,

    If the memory device supports qspi with XIP then I don't see why it would not work in this case. Please take a look at our TRM, more specifically section 12.3.2.4.9 OSPI Direct Access Controller (DAC). The Direct Access Controller can be used to both access and execute code from external Flash memory.

    As previously mentioned, the AM243x does not have MRAM/FRAM capabilities so keep in mind you would be limited by the flash-specific API.

    Best,

    Daniel

    Link to the TRM: AM64x /AM243x Processors Silicon Revision 2.0 Texas Instruments Families of Products (ti.com)

  • 0 in reply to Daniel Bermudez
    Prodigy 210 points

    Hi Daniel,

    Can i find anywhere which SPI command codes and protocol (4s-4s-4s)? are used for read/writes in memory mapped mode?

    best regards,

    Tom

  • 0 in reply to tom
    TI__Expert 7630 points

    Hi Tom,

    The DAC will still operate under the SPI controller's protocols. You have to make sure that the flash memory that you are using has commands that operate in the same OSPI protocols that you want to operate in. This also depends on whether you are using SDR or DDR communication. 

    Table 12-3304. READ and WRITE Instruction Configuration of the TRM shows how software should configure the OSPI module for selected specific READ and WRITE instructions. With this information in hand, now you have to find the corresponding info in the flash's datasheet. For example, on a the W25Q64JV QSPI memory (W25Q64JV Datasheet (mouser.cn)) the details get presented the following way:

    Hope this helps, if you have any more specific questions please don't hesitate on posting them.

    Best,

    Daniel

  • 0 in reply to Daniel Bermudez
    Prodigy 210 points

    Hi Daniel,

    So if i understand you correctly the DAC is using the Flash API and it's driver configuration?

    My only question is then how the erase/blocks are handled.

    Does it do block/sector erases?

    If so is it possible to disable this?

    best regards,

    Tom

  • 0 in reply to tom
    TI__Expert 7630 points

    The way it operates is that in Direct Access mode the CPU or DMA accesses the memory address, but the device still uses the OSPI Controller to write that information to the flash device since there are no parallel lines of communication between OSPI memory and MCU Device. DAC (memory mapped mode) just presents an easier way of talking the external flash memory

    A separate software controller (STIG - Software Triggered Instruction Generator) actually takes care of performing ERASE functions. The STIG is controlled using the OSPI_FLASH_CMD_CTRL_REG register by setting up the command to issue to the FLASH device. This is a generic controller and can be used to perform any instruction that the FLASH device supports from the extended SPI protocol. Section 12.3.2.4.11 OSPI Software-Triggered Instruction Generator (STIG) of the TRM goes over more information on this.

    So yes, you can issue block and sector erases with the correct instruction and using the OSPI_FLASH_CMD_CTRL_REG register.

    tom said:
    If so is it possible to disable this?

    do you mean disabling the block erase? keep in mind that erasing the memory space before writing to the same space is a requirement in most flash memories. Not calling the instruction should be enough from preventing its execution

    Best,

    Daniel