EK-TM4C123GXL: ADC Sample Sequence Config

Kevin Hinrichs

Part Number: EK-TM4C123GXL

Hi,

I have a question about the sample sequencer.
I am concerned about the sequence.
If I set an END flag after each sequence, does this mean that only ONE trigger performs ONE sequence.
And only a REPEATED trigger the next sequence?
As an example below the code.
The trigger must fire four times so that 4 samples are stored?
And only then an interrupt comes e.g. for the uDMA to transport these 4 samples from the FIFO into the SRAM.
And so on.

MAP_ADCSequenceConfigure(ADC0_BASE, 0, ADC_TRIGGER_TIMER, 0);
MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH5 | ADC_CTL_END);
MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH5 | ADC_CTL_END);
MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH5 | ADC_CTL_END);
MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 3, ADC_CTL_CH5 | ADC_CTL_IE) | ADC_CTL_END);
MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 4, ADC_CTL_CH5 | ADC_CTL_END);
MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 5, ADC_CTL_CH5 | ADC_CTL_END);
MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 6, ADC_CTL_CH5 | ADC_CTL_END);
MAP_ADCSequenceStepConfigure(ADC0_BASE, 0, 7, ADC_CTL_CH5 | ADC_CTL_IE | ADC_CTL_END);

over 2 years ago

0 Ralph Jacobi over 2 years ago

TI__Guru*** 135355 points

Hello Kevin,

Using ADC_CTL_END will end the sequence at that step and it won't progress to future steps.

I'm not really sure what specifically you are trying to achieve but here is an example of how to setup a multi-channel ADC sequence:

    /* Configure step 0, 1, 2, 3 on sequence 0.  Sample channel 0, 1, 2 ,3 in
     * single-ended mode (default) and configure the interrupt flag
     * (ADC_CTL_IE) to be set when the channel 3 is done.  Tell the ADC logic
     * that this is the last conversion on sequence 3 (ADC_CTL_END). */
    ADCSequenceStepConfigure(ADC0_BASE, 0, 0, ADC_CTL_CH0 );
    ADCSequenceStepConfigure(ADC0_BASE, 0, 1, ADC_CTL_CH1 );
    ADCSequenceStepConfigure(ADC0_BASE, 0, 2, ADC_CTL_CH2 );
    ADCSequenceStepConfigure(ADC0_BASE, 0, 3, ADC_CTL_CH3 | ADC_CTL_IE |
                             ADC_CTL_END );

Best Regards,

Ralph Jacobi

0 Kevin Hinrichs over 2 years ago in reply to Ralph Jacobi

Prodigy 180 points

First of all I would like to thank you for always helping me in this forum!
I always want to record one sample per timer trigger. These samples should be transported over uDMA to the SRAM. A total of 1024 samples should be transferred via uDMA in PING PONG mode. The documentation says:
The arbitration size of the μDMA transfer must be a power of 2, and the corresponding IE bits in the ADCSSCTLn register must be set. Does this mean that I always have to transfer 2 samples? I want to make this process as resource reducing as possible and use the burst mode efficent with uDMA.

0 Ralph Jacobi over 2 years ago in reply to Kevin Hinrichs

TI__Guru*** 135355 points

Hello Kevin,

The timer trigger vs the uDMA transfer are separate elements. You can use uDMA burst mode to transfer multiple bytes of sensor data efficiently for your use case.

I would recommend you review our TivaWare example adc_udma_pingpong. From your description, it sounds nearly identical to the example which triggers a single conversion each timer trigger and then transfers them in bulk with the uDMA interface using burst mode.

Best Regards,

Ralph Jacobi

0 Kevin Hinrichs over 2 years ago in reply to Ralph Jacobi

Prodigy 180 points

Thank you very much for your answer.

Please believe me, I have watched the documentary, the driverlib and the examples all several times. These are also very helpful.
But in this example is also taken as arbsize 1. That means 1 item per trigger. and I thought that would be inefficient.
I understood the SS0 as a kind of FIFO, which I can fill with 4 samples and then tell the udma to send 4 samples.
But the SSn is good for processing multiple analog inputs with one trigger. but not good to trigger one analog inpput.
I had completely misunderstood.
Thank you!

I still have questions about this.
If I want to record an analog input with as different sample rates as possible.
The recordings should run as parallel as possible. Which possibilities do I have?
I see I have following triggers:
ADC_TRIGGER_PWM0,
ADC_TRIGGER_PWM1,
ADC_TRIGGER_PWM2,
ADC_TRIGGER_PWM3
I have 4 sample sequencers.
That means I can trigger an analog input in parallel with four different sample rates via the PWMn?
Can I also set ADC0 and ADC1 respectively?
That would mean that I have 8 different sample rates for one analog input in parallel?

The next thing I still don't understand is.
If I set an ADC sample rate of 500Msps, but only need a sample rate of 44,1ksps.
Can I enable hardware oversampling?
And if I switch it on e.g. to 8.
Then the rate would be 500ksps/16=62,5ksps.
This would still be faster than if I pick up samples from a timer every 44.1khz.
or do I have to set the timer 44,1khz * 8 ?
I don't understand the connection between a sample rate of 1Msps or e.g. 500ksps and a timer that I have set to 44,1khz. Since the overriding clock is faster than my actual sample rate I have set as trigger for the adc.
If I don't need to sample that fast, what's the point of taking the sample rate from the adc down from 1Msps to 500ksps or even less?

+1 Ralph Jacobi over 2 years ago in reply to Kevin Hinrichs

TI__Guru*** 135355 points

Hi Kevin,

I honestly haven't done something like what you are describing with notably different sample rates but the one thing I don't think would work is to do that on the same input channel unless you are cascading your triggers somehow.

What I would expect to do instead is have a different trigger on the four different sample sequences with each sequence reading from a different ADC channel.

I don't really see a means to do 4 or 8 samples at different rates on a single input, much less in parallel.

Kevin Hinrichs said:
If I set an ADC sample rate of 500Msps, but only need a sample rate of 44,1ksps.
Can I enable hardware oversampling?
And if I switch it on e.g. to 8.
Then the rate would be 500ksps/16=62,5ksps.
This would still be faster than if I pick up samples from a timer every 44.1khz.
or do I have to set the timer 44,1khz * 8 ?

For ADC Oversampling theory, I would recommend you read this document: https://www.ti.com/lit/pdf/spma001

Oversampling isn't about speed but increasing accuracy, so your comments don't really align with the benefit you gain from oversampling.

I don't think you need to focus so much on the ADC sample rate you have set. It's kind of like the system clock. You set it to a high rate (80MHz) so you are not limited by the base ADC sample rate but can use lower instances. Thats why its just called 'maximum sample rate' because you don't always have to use the max.

Best Regards,

Ralph Jacobi

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EK-TM4C123GXL: ADC Sample Sequence Config