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AM2434: Pin mapping for PRU_ICSSG MII signals

Part Number: AM2434
Other Parts Discussed in Thread: SYSCONFIG

Our customer is routing their board but is stalled.

For PRU_ICSSG MII signals, it seems that the pin mapping generated by SysConfig tool is different from the pin mapping in "Table 6-455. PRU_ICSSG0 I/O Signals" on the TRM, and that the 0 and 1 pin mapping is swapped for the Tx signals.

The pin mapping generated by the SysConfig tool is attached here: AM243x ALV ICSSG MII IO Signals in SysConfig.xlsx

The pin mapping in "Table 6-455. PRU_ICSSG0 I/O Signals" on the TRM is attached here: AM243x ALV ICSSG MII IO Signals in TRM.xlsx

The routing for the MII signals which are pin-multiplexed with RGMII signals on TMDS243GPEVM seems to match the pin mapping generated by the SysConfig tool.

The mapping generated by the SysConfig tool seems to be correct from the correspondence between the MII signals and the pin-multiplexed RGMII signals.

Is the pin mapping for PRU_ICSSG MII signals generated by the SysConfig tool correct?

Is the pin mapping for PRU_ICSSG MII signals in "Table 6-455. PRU_ICSSG0 I/O Signals" on the TRM incorrect?

Best regards,

Daisuke

  • Hello Daisuke,

    The ICSS pin mapping provided in the TRM is part of the original HW definition of the PRU_ICSSG. However, due to the flexibility provided by the IP and associated FW configuraitons, this is not necessarily a hard requirement. The first PRU_ICSSG implementation for AM65x had the MII TX pins swapped during initial SoC integration and this convention was maintained for subsequent ICSS revisions to enable firmware reuse. In order to make use of the SDK firmware, the SysConfig generated pin configuration should be used.

    Regards,

    Erik

  • Hi Erik-san,

    Thank you for your reply.

    I understand that the PRU_ICSSG pin mapping provided in the TRM is correct at the HW level, but please update the TRM so that it does not confuse users by being different from the pins used by the FW.

    Best regards,

    Daisuke