• State TI Thinks Resolved
  • Locked Locked
  • Replies 11 replies
  • Answers 1 answer
  • Subscribers 31 subscribers
  • Views 647 views
  • Users 0 members are here
Support feedback
Options
Options
Related

This thread has been locked.

If you have a related question, please click the "Ask a related question" button in the top right corner. The newly created question will be automatically linked to this question.

AM263x SPI Chip-select TCS issue

Gianni Perugini
Prodigy 130 points
Other Parts Discussed in Thread: SYSCONFIG

Dear all,

we need to use SPI in our project. To achieve this task, we imported the example project 'mcspi_loopback_am263x-cc_r5fss0-0_freertos_ti-arm-clang' first to test SPI controller.

We noticed a possible issue on the generated signal. 

Attached you can find the example.syscfg pictures to show how the SPI is configured.

Below the picture with the captured signals (yellow is the CLK while green is the CS)

As you can see from configuration SPI frequency clock is 50 Mhz so we have a tclk = 20ns.

Since Chip select TCS is set to 0 it means 0.5 clock cycles delay; so we expect to have a delay of 10ns while we have a delay of 3us as you can see from the above picture.

Could you help us please?

Waiting for your kind reply

Thanks

BR

Gianni

  • 0
    TI__Expert 6965 points

    Hello Gianni,

    I apologize for the delay, I am going to setup this up on my control card and confirm this behavior. I agree with your assessment so far and so I'd like to make sure that it can be replicated. 

    Regards,

    Erik

  • 0 in reply to Erik Friedel
    Prodigy 130 points

    Hello Erik,

    thanks for your answer.

    Please let me know if you can replicate this behaviour and if there is a possible workaround.

    Regards

    Gianni

  • 0 in reply to Gianni Perugini
    TI__Expert 6965 points

    Hello Gianni,

    I was able to run the same SPI loopback test and can confirm the behavior that you are observing. It seems like the delay is ~3uS regardless of the clock speed. I will contact experts from the SDK team and see if this is expected behavior for the SPI loopback test. 

    Regards,

    Erik

  • 0 in reply to Erik Friedel
    Prodigy 130 points

    Hello Erik,

    have you got any news?

    Regards

    Gianni

  • 0 in reply to Gianni Perugini
    TI__Expert 6965 points

    Hello Gianni,

    First, make sure that you are using the 8.4 release of the MCU+SDK as there have been some performance improvement updates for this example. 

    In the loobpack example, the CS is asserted manually by writing to the force bit in the CH conf register. This is done to keep CS asserted across multiple words. The delay from CS assertion to the first clock is the difference between writing to the CH conf register to assert force bit to writing the first word in the Tx register. 

    The delay that is being observed is caused by using interrupt mode. After the MCSPI channel is enabled, the interrupt is triggered and within the interrupt service routine (ISR) call the Tx register is written.

    To reduce the ISR call delay, you can switch the operating mode from "Interrupt Mode" to "Polled Mode". 

    Regards,

    Erik

  • 0 in reply to Erik Friedel
    Prodigy 130 points

    Hello Erik,

    Thanks for the answer. We expected that the CS was managed by SPI controller without any software intervention. And the question is: why is possible to change the Chip-select TCS in the sysconfig if this feature is not used?

    Regards

    Gianni

  • 0 in reply to Gianni Perugini
    Prodigy 130 points
    Gianni Perugini said:
    We expected that the CS was managed by SPI controller without any software intervention. And the question is: why is possible to change the Chip-select TCS in the sysconfig if this feature is not used?

    Dear all,

    could someone reply to this point, please?

    Thanks

    BR

    Gianni

  • 0 in reply to Gianni Perugini
    TI__Expert 6965 points

    Hello Gianni,

    I am still awaiting feedback from the SDK team for this information. I will respond to this thread with that information as soon as possible. 

    Regards,

    Erik

  • 0 in reply to Erik Friedel
    Prodigy 130 points

    Hello Erik,

    thanks for your reply.

    I look forward to hearing from you.

    Regards

    Gianni

  • 0 in reply to Gianni Perugini
    TI__Expert 6965 points

    Hello Gianni,

    I cannot provide exact measurements at this point but the delay that is being observed is due to software overhead involved with the interrupts being used to drive the example. The half clock cycle TCS value can be true while not being observed in this example as it is a hardware specification. Is there a specific value for the delay between CS and first clock cycle that you are trying to achieve?

    EDIT: It is possible to get a half clock cycle delay with the AM263x CC and the MCSPI Loopback demo. There are two SYSCONFIG configurations needed:

    1) Set mode of operation to Multi Master

    2) Set Operating mode to polled mode

    Here is a capture showing a half clock cycle delay (10nS) at 50MHz with these configurations:

    Regards,

    Erik

  • 0 in reply to Erik Friedel
    Prodigy 130 points

    Hello Erik,

    thanks for your reply.

    Erik Friedel said:
    Is there a specific value for the delay between CS and first clock cycle that you are trying to achieve?

    Yes of course, in terms of performance, I expected that there is as little time as possible. Since Chip select TCS should be at least 0.5 clock cycles delay (with a clock of 50 Mhz), I expected that time was 10ns instead of 3us! 

    Regards

    Gianni