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LP-MSPM0L1306: Flash programming cause SoC AHB bus to be inaccessible

Jaka Jemec
Prodigy 115 points
Part Number: LP-MSPM0L1306

After programming something to the address 0x00000000 (flash), the size doesn't matter, the SoC became inaccessible. If I do flash mass erase and assert reset, the AHB bus is accessible again and SoC can be halted with writhing to DHCSR, stepping and that stuff. But if I program the address 0x00000008 or above, everything works and AHB bus is still accessible after reset, mass erase isn't needed.

Is the first 64 bits of the flash checked at boot process and when addresses 0x00000000-0x00000008 is not erased, this locks the bus? 

One additional question:

When I download code to ram and run, after ~7 seconds the reset automatically happens and the VCATCH bit in DFSR(0xE000ED30) is set. This is not related with the code that is executed, even looping while(1) this occur. Watchdog is disabled and from status register can confirm that watchdog is not the cause of this.


Thank and have a nice day,
Jaka

  • 0
    TI__Mastermind 21400 points

    Hi Jaka,

    The compiler will default to use the first sectors of FLASH, so when you erase the first sector in flash it will erase all your code and replace it with 0xFFFFFFFF. This erases the currently running code so the CPU can't perform the next command. You can use the memory browser to observe this, set a breakpoint at the flash erase and when you step though you can see your current code get erased. If you check the disassembly you can see the compiled code also get erased. If you're storing data I recommend to do it in the back of FLASH to avoid this.

    Is the ram code the same one where you program the first sector of flash? 

    Regards,

    Luke

  • 0 in reply to Luke Ledbetter
    Prodigy 115 points

    We don't understand each other. If the first address is everything else than 0xFFFFFFFF, the SoC state cant be observed via AHB bus. Before reading this on AHB bus, I need to perform System reset with writing to SYSCTL_RESETCMD to execute CPU reset. It is possible that at the Boot the SoC checks the first 64 bits of flash and depending on the value it allows or blocks the debug connection.

    Yes Ram code is the same only linked to ram and not to flash.

    Best regards, Jaka

  • 0 in reply to Jaka Jemec
    TI__Mastermind 21400 points

    Hi Jaka,

    Maybe I'm misunderstanding your application. I thought you were doing flash writes to the memory location of 0x00000000. Can you share a simple test case for your program that will demonstrate this? This will let me step through and observe what you're seeing on your end.

    Regards,

    Luke