MSPM0L1105: MSPM0G310x download fail first time when MCLK source from SYSPLL

Hi there,

Is the program in low power mode before programming?

I will try to reproduce the issue and get back to you later

Thanks

Yuhao

Hi YuHao,

       The chip runs in sleep0 mode. All syscfg file content show below:

/**
* These arguments were used when this file was generated. They will be automatically applied on subsequent loads
* via the GUI or CLI. Run CLI with '--help' for additional information on how to override these arguments.
* @cliArgs --device "MSPM0G350X" --package "LQFP-64(PM)" --part "Default" --product "mspm0_sdk@0.50.00.01"
* @versions {"tool":"1.14.0+2667"}
*/

/**
* Import the modules used in this configuration.
*/
const SYSCTL = scripting.addModule("/ti/driverlib/SYSCTL");
const SYSTICK = scripting.addModule("/ti/driverlib/SYSTICK");

/**
* Write custom configuration values to the imported modules.
*/
SYSCTL.useHFCLK_Manual = true;
SYSCTL.HFCLKSource = "HFXT";
SYSCTL.HFCLK_Freq = 16000000;
SYSCTL.HFXTStartup = 10;
SYSCTL.HFCLKMonitor = true;
SYSCTL.EXCLKSource = "SYSPLLOUT1";
SYSCTL.HSCLKSource = "SYSPLLCLK2X";
SYSCTL.SYSPLLSource = "HFCLK";
SYSCTL.SYSPLL_CLK2XEn = true;
SYSCTL.SYSPLL_Qdiv = 5;
SYSCTL.MCLKSource = "HSCLK";
SYSCTL.SYSPLL_Pdiv = 2;
SYSCTL.UDIV = "2";

const Board = scripting.addModule("/ti/driverlib/Board", {}, false);

SYSTICK.periodEnable = true;
SYSTICK.interruptEnable = true;
SYSTICK.systickEnable = true;
SYSTICK.period = 800000;

/**
* Pinmux solution for unlocked pins/peripherals. This ensures that minor changes to the automatic solver in a future
* version of the tool will not impact the pinmux you originally saw. These lines can be completely deleted in order to
* re-solve from scratch.
*/
SYSCTL.peripheral.$suggestSolution = "SYSCTL";
SYSCTL.peripheral.hfxInPin.$suggestSolution = "ball.45";
SYSCTL.peripheral.hfxOutPin.$suggestSolution = "ball.46";
Board.peripheral.$suggestSolution = "DEBUGSS";
Board.peripheral.swclkPin.$suggestSolution = "ball.13";
Board.peripheral.swdioPin.$suggestSolution = "ball.12";

Best regards,

Jason

Hi Jason,

I guess that you want to config 80Mhz for SYSPLL. So maybe there is a little error:

 'SYSCTL.SYSPLL_Qdiv = 5;'

The desired QDIV divider is selected by programming 0x01 to 0x7F for /2 to /128. (You can find in Page 68 of user guide)

So QDIV should be 4.

Thanks

Yuhao

Hi YuHao,

This is a feature of the sysconfig tool. The syscfg file shows 5, and the generated code is 4. I have tried to configure the MCLK to be 64M or lower, which also has the problem. The following code is generated for the syscfg file in the previous reply.

Best regards,

Jason

#include "ti_msp_dl_config.h"

/*
* ======== SYSCFG_DL_init ========
* Perform any initialization needed before using any board APIs
*/
SYSCONFIG_WEAK void SYSCFG_DL_init(void)
{
SYSCFG_DL_initPower();
SYSCFG_DL_GPIO_init();
/* Module-Specific Initializations*/
SYSCFG_DL_SYSCTL_init();
SYSCFG_DL_SYSTICK_init();
SYSCFG_DL_SYSCTL_CLK_init();
}

SYSCONFIG_WEAK void SYSCFG_DL_initPower(void)
{
DL_GPIO_reset(GPIOA);
DL_GPIO_reset(GPIOB);

DL_GPIO_enablePower(GPIOA);
DL_GPIO_enablePower(GPIOB);

delay_cycles(POWER_STARTUP_DELAY);
}

SYSCONFIG_WEAK void SYSCFG_DL_GPIO_init(void)
{
/* Configure GPIO/IOMUX for HFXT functionality */
DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXIN_IOMUX);
DL_GPIO_initPeripheralAnalogFunction(GPIO_HFXOUT_IOMUX);

}

static const DL_SYSCTL_SYSPLLConfig gSYSPLLConfig = {
.inputFreq = DL_SYSCTL_SYSPLL_INPUT_FREQ_8_16_MHZ,
.rDivClk2x = 0,
.rDivClk1 = 0,
.rDivClk0 = 0,
.enableCLK2x = DL_SYSCTL_SYSPLL_CLK2X_ENABLE,
.enableCLK1 = DL_SYSCTL_SYSPLL_CLK1_DISABLE,
.enableCLK0 = DL_SYSCTL_SYSPLL_CLK0_DISABLE,
.sysPLLMCLK = DL_SYSCTL_SYSPLL_MCLK_CLK2X,
.sysPLLRef = DL_SYSCTL_SYSPLL_REF_HFCLK,
.qDiv = 4,
.pDiv = DL_SYSCTL_SYSPLL_PDIV_2,

};
SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_init(void)
{
DL_SYSCTL_setSYSOSCFreq(DL_SYSCTL_SYSOSC_FREQ_BASE);
DL_SYSCTL_setHFCLKSourceHFXTParams(DL_SYSCTL_HFXT_RANGE_8_16_MHZ, 10, true);
DL_SYSCTL_configSYSPLL((DL_SYSCTL_SYSPLLConfig *) &gSYSPLLConfig);

DL_SYSCTL_setMCLKSource(SYSOSC, HSCLK, DL_SYSCTL_HSCLK_SOURCE_SYSPLL);
DL_SYSCTL_setMCLKDivider(DL_SYSCTL_MCLK_DIVIDER_DISABLE);
DL_SYSCTL_setULPCLKDivider(DL_SYSCTL_ULPCLK_DIV_2);
DL_SYSCTL_setBORThreshold(DL_SYSCTL_BOR_THRESHOLD_LEVEL_0);
DL_SYSCTL_setFlashWaitState(DL_SYSCTL_FLASH_WAIT_STATE_2);

}
SYSCONFIG_WEAK void SYSCFG_DL_SYSCTL_CLK_init(void) {
while ((DL_SYSCTL_getClockStatus() & (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
| DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
| DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
| DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
!= (DL_SYSCTL_CLK_STATUS_SYSPLL_GOOD
| DL_SYSCTL_CLK_STATUS_HFCLK_GOOD
| DL_SYSCTL_CLK_STATUS_HSCLK_GOOD
| DL_SYSCTL_CLK_STATUS_LFOSC_GOOD))
{
;
}
}

SYSCONFIG_WEAK void SYSCFG_DL_SYSTICK_init(void)
{
/*
* Initializes the SysTick period to 10.00 ms,
* enables the interrupt, and starts the SysTick Timer
*/
DL_SYSTICK_config(800000);
}