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TMDS273GPEVM: AM2732 CSI-RX firmware integration problem.

Alessandro Spinetti
Prodigy 60 points

Part Number: TMDS273GPEVM

Hi TI experts,

I'm trying to connect the Sitara eval module to an our custom board with CSI IF.

In order to check the connection, I'm using the CSI-RX examples under the mcu plus sdk version 08.04.00.17.

As written in the SDK, this example is not working with an external CSI2 device but it's working only internally. 

We modified the example code to work with the custom board but it's not working.

The CSI on the custom board has this parameters:

- 2 data lanes (D0 and D1)

- 1 CLK lane with freq of 160MHz (320Mbps each lane).

- the CSI IF is connected to the connector J1 of the Front end 1.

I've checked the CSI with oscilloscope and it runs as expected.

Regarding the code these are the steps made:

1) Import the example with CCS  Version: 11.2.0.00007

2) commented the part of "CSIRX_debugModeGenerateFrames" and "CSIRX_debugModeEnable"

3) changed the configuration with sysvconfig to match the HW

4) added two more interrupts for the Line Start Detect and Frame Start Detect.

With this code no interrupts was generated even if the CSI is running.

What I should check in the firmware to debug the problem?

In which document I can find the correspondence between the Data Lane Config Position of the sysconfig and the real pin of the device?

Thanks.

  • 0
    TI__Mastermind 18470 points

    Hi Alessandro, 

    Can you provide any further info on the specific CSI TX IP being integrated with the CSI RX of the AM273x? Can you also provide the data lane/clock lane mapping that is needed?

    Thank you,

    -Randy

  • 0 in reply to Randy Rosales
    Prodigy 60 points

    HI Randy,

    We use a Crosslink FPGA and we use their IP named "CSI-2/DSI D-PHY Transmitter v1.4" that is compatible with MIPI CSI-2 v1.1.

    The configuration that we used are these:

    - Number of TX lanes = 2 

    - Baud rate = 162Mbps x lanes

    - D-PHY Clock frequency = 81MHz

    - D-PHY clock mode = Continous

    In the CCS project I've configured the Data Lanes as is visible in the image below.

    Also for the Data Lane 3 was NOT_USED.

    I've configured in this way because I need this configuration:

    Data Lane 0 -> to pin B7/A7 of the Sitara

    Data Lane 1 -> to pin A5/B5 of the Sitara

    Clock Lane -> to pin A6/B6 of the Sitara

    Is it correct? I can't find information regarding the equivalence between LANE_POSITION and pin of the IC. Could you explain?

    Other than that we use DataType of the CSI protocol equal to 0x2A (RAW8) and Virtual channel = 1 in the FPGA and I've configured the same parameters in the sysconfig tab.

    I've also enabled interrupt for frame start and line start event but no interrupt was recognized. 

    Thank you.

  • 0 in reply to Alessandro Spinetti
    TI__Expert 8550 points

    Hi, the mapping looks incorrect, could you please refer to Table Table 6-3. Signal Descriptions in the Data Sheet https://www.ti.com/lit/ds/symlink/am2732.pdf? ?

    Best Regards, Shiv

  • 0 in reply to Shivasharan Nagalikar
    Prodigy 60 points

    Hi Shiv,

    thanks for your reply.

    I'm using CCS version 11.2.0.00007 and Sysconfig script file with only this option for CSI pins:

    Which of this values matches the CLK pin?

    And also I need to exchange some data lanes due to the connector connections, is it possible? If not what is the meaning of the Position field?

    Thanks.

  • 0 in reply to Alessandro Spinetti
    TI__Expert 8550 points

    Hi , ok I see your point. I will confirm with the CSI experts and comeback. Is there a chance you could provide the full sysconfig file  or have full config dump of CSI ?

    Best Regards, Shiv

  • 0 in reply to Shivasharan Nagalikar
    Prodigy 60 points

    Hi,

    I've attached the sysconfig file I used (I've zipped, otherwise I cannot insert). It was modified starting from the CSI_RX example of the AM273x MCU+SDK 08.04.00 package.

    Thanks, 

    Regards.

    5315.example.zip

  • 0 in reply to Alessandro Spinetti
    TI__Expert 8550 points

    Hi, the config file looks fine (Except clock lane is missing). I got the confirmation that the Lane could be exchanged. Can you also please provide the dump of CSI registers after sending the data from other side ? 

    Best Regards, Shiv

  • 0 in reply to Shivasharan Nagalikar
    Prodigy 60 points

    Hi Shiv,

    I've attached the dump of the CSI registers.

    Fullscreen CSI2_reg_export.txt Download 
    521177 13
R RCSS_CSI2A_CSI2_REVISION 0x0000000B 0x00000030
R RCSS_CSI2A_CSI2_SYSCONFIG 0x0000000B 0x00000001
R RCSS_CSI2A_CSI2_SYSSTATUS 0x0000000B 0x00000001
R RCSS_CSI2A_CSI2_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTRL 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_DBG_H 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_GNQ 0x0000000B 0x0000001B
R RCSS_CSI2A_CSI2_COMPLEXIO_CFG2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_COMPLEXIO_CFG1 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_COMPLEXIO1_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_COMPLEXIO2_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_SHORT_PACKET 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_COMPLEXIO1_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_COMPLEXIO2_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_DBG_P 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_TIMING 0x0000000B 0x7FFF7FFF
R RCSS_CSI2A_CSI2_CTX0_CTRL1 0x0000000B 0x00010008
R RCSS_CSI2A_CSI2_CTX0_CTRL2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX0_DAT_OFST 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX0_DAT_PING_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX0_DAT_PONG_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX0_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX0_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX0_CTRL3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_CTRL1 0x0000000B 0x00010008
R RCSS_CSI2A_CSI2_CTX1_CTRL2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_DAT_OFST 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_DAT_PING_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_DAT_PONG_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_CTRL3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_CTRL1 0x0000000B 0x00010008
R RCSS_CSI2A_CSI2_CTX2_CTRL2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_DAT_OFST 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_DAT_PING_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_DAT_PONG_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_CTRL3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_CTRL1 0x0000000B 0x00010008
R RCSS_CSI2A_CSI2_CTX3_CTRL2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_DAT_OFST 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_DAT_PING_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_DAT_PONG_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_CTRL3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_CTRL1 0x0000000B 0x00010008
R RCSS_CSI2A_CSI2_CTX4_CTRL2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_DAT_OFST 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_DAT_PING_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_DAT_PONG_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_CTRL3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_CTRL1 0x0000000B 0x00010008
R RCSS_CSI2A_CSI2_CTX5_CTRL2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_DAT_OFST 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_DAT_PING_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_DAT_PONG_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_CTRL3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_CTRL1 0x0000000B 0x00010008
R RCSS_CSI2A_CSI2_CTX6_CTRL2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_DAT_OFST 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_DAT_PING_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_DAT_PONG_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_CTRL3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_CTRL1 0x0000000B 0x00010008
R RCSS_CSI2A_CSI2_CTX7_CTRL2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_DAT_OFST 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_DAT_PING_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_DAT_PONG_ADDR 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_IRQENABLE 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_IRQSTATUS 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_CTRL3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_PHY_CFG_REG0 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_PHY_CFG_REG1 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_PHY_CFG_REG2 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_PHY_CFG_REG3 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_PHY_CFG_REG4 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_PHY_CFG_REG5 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_PHY_CFG_REG6 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX0_TRANSCODEH 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX0_TRANSCODEV 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_TRANSCODEH 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX1_TRANSCODEV 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_TRANSCODEH 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX2_TRANSCODEV 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_TRANSCODEH 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX3_TRANSCODEV 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_TRANSCODEH 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX4_TRANSCODEV 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_TRANSCODEH 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX5_TRANSCODEV 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_TRANSCODEH 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX6_TRANSCODEV 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_TRANSCODEH 0x0000000B 0x00000000
R RCSS_CSI2A_CSI2_CTX7_TRANSCODEV 0x0000000B 0x00000000

    I've made it in debug mode with CCS.

    Thanks.

  • 0 in reply to Alessandro Spinetti
    TI__Expert 8550 points

    Hi,

    Thanks for the dump. Let me check and come back.

    Best Regards, Shiv

  • 0 in reply to Shivasharan Nagalikar
    TI__Expert 8550 points

    Hi,

    Sorry for the delay here as I am working with CSI experts on the dump. Will update as soon as I make some progress on this.  

    Best Regards, Shiv

  • 0 in reply to Shivasharan Nagalikar
    TI__Mastermind 35265 points

    Hello Alessandro,

    Could you please refer to the thread (17) AWR2944: receive data from CSI2 - Sensors forum - Sensors - TI E2E support forums
    as it looks like a similar query.

    Regards,
    Saswat Kumar

  • 0 in reply to Saswat Kumar
    Prodigy 60 points

    Hi Saswat,

    Thanks for the reply, I've read the thread and in that case the problem was due to the FPGA output that didn't generates the right data. Due to this, I've checked the output data coming from the FPGA. 

    I've attached an image from our oscilloscope, the green and yellow lines are Data0 and Data1 lanes of the CSI (only the negative part of the differential pairs). To acquire this data I've reduced as much as possible the datarate down to 160Mbps (80MHz DDR clock). 

    Decoding and evaluate these streams I obtain good results, at least for the short packet. In both lanes I was able to find the SoT sync data (00011101) and after that I obtain reasonable values for the DATA_ID, WORD_COUNT and ECC fields.

    In the image above we have a Frame Start Short Packet and a Line Start Short Packet.

    So, at least for the SP, the FPGA sent the right values, but in the Sitara code I can't trigger any interrupt.

  • 0 in reply to Alessandro Spinetti
    TI__Expert 8550 points

    Hi Alessandro,

    Apologies for delayed response on this.

    From the provided register dump (13th Jan post above) , it looks like the registers are not properly programmed or you are taking the register dump at the wrong time. In the dump, RCSS_CSI2A_CSI2_CTRL  shows all zeros. Please try to take the register dump just after configuring the CSIRX. You can refer to to AM273X Technical Reference Manual, section 10.6.1.1.3.5 ,for understanding about the CSIRX registers. While enabling the interrupts, please also make sure to enable the error interrupts so that we can have more information on the issue. And you are using instance A ?

    Best Regards, Shiv

  • 0 in reply to Shivasharan Nagalikar
    Prodigy 60 points

    Hi Shiv,

    I've already taken this register dump just after the configuration. Anyway I saw the bit 0 of the RCSS_CSI2A_CSI2_CTRL, the IF_EN will remain 0.

    I debug a little bit and it's due to a problem on "Drivers_csirxInstanceOpen",  when the code executes the "CSIRX_complexioIsResetDone" the flag RESET_DONE of the CSI2_COMPLEXIO_CFG1 register never became 1.

    Due to this the code exits with an error.

    Why this reset bit is not cleared?

    Yes, I'm using instance A.

    Thanks.

    Regards.

  • 0 in reply to Alessandro Spinetti
    TI__Expert 8550 points

    Hi Alessandro,

    Is there a chance you could share the example code that you are using ?

    Best Regards, Shiv

  • 0 in reply to Shivasharan Nagalikar
    Prodigy 60 points

    Hi Shiv,

    sure, I'v attached an archive with the code of the example. I've made only some modification to reset my HW.

    Thanks.

    csirx_internal_capture_am273x-evm_r5fss0-0_nortos_ti-arm-clang.zip

  • 0 in reply to Alessandro Spinetti
    TI__Expert 8550 points

    Thanks Alessandro,

    We will check and comeback. Do you mean with the modification you are able to reset the HW but still you see the issue ?

    Best Regards, Shiv

  • 0 in reply to Shivasharan Nagalikar
    Prodigy 60 points

    Hi Shiv,

    yes. I made the reset after AM2732 CSI init as suggested but the issue didn't solve.

    Thanks.

    BR.

  • 0 in reply to Alessandro Spinetti
    Prodigy 60 points

    Hi Shiv,

    do you have any feedback on this topic ? Did you have time to analyze the shared source code?

    Thanks.

    BR.

  • 0 in reply to Alessandro Spinetti
    TI__Expert 8550 points

    Hello Alessandro,

    Apologies for the long delay between replies. After receiving the software project and reviewing the details, our intentions had been to leverage it to accelerate the debug and provide a working solution. Unfortunately it has become clear that we are not in a position to accurately deep dive this particular issue at this time due to the complexity of the CSI-RX interface. We plan to address this gap in our support capabilities at some point in the future, but regarding your specific question we are unfortunately unable to provide any deeper support at this time. This is not the answer we wanted to reach on this topic and I apologize for it dragging out only to arrive at this unfortunate conclusion.

    Best Regards, Shiv