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AM2632: Is it possible to manage multiple GPIO pin interrupts on the same bank?

GIOVANNI STOPPONI
Prodigy 40 points
Part Number: AM2632


Hello,

I need to manage 5 gpio pin interrupts on bank 7 and 4 gpio pin interrupts on bank 6.

From the "gpio_input_interrupt_am263x" example in the SDK, I understood that the AM2632 manages the GPIO ISR at bank level (each bank includes 16 pins), therefore if we have to monitor more than 1 GPIO on the same BANK we have to read the gpio to check which GPIO was triggering the interrupt. But, if the connected signals change very fast, it is possible that we can't find the pin which triggered the interrupt.

Furthrermore, in case of simultaneous triggering, we can't know which GPIO pin triggered the interrupt first.

Please, answer this question:

1) is it possible to trigger a different ISR for each different pin of the same bank?

2) in that case can you provide a general example with at least 2 GPIO of the same bank that will trigger 2 different ISR?

Best Regards.

GS

  

  • 0
    TI__Mastermind 23423 points

    Hello Giovanni,

    We are looking into your query and will reply with additional details once available. Initial thoughts: due to the grouping of GPIO interrupt events, it will not be possible to have a per pin ISR. One possibility might be to spread the IO signals across GPIO banks so that each per-bank interrupt is associated with the specific IO event.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 40 points

    Hello Fleenor,

    we need to monitor 11 gpio pins for a rise/fall edge and we need to know which is the first event.

    The AM2632 includes only 9 banks, therefore we can't spread the IO signals across GPIO banks.

    The pulses may be very short, therefore we don't want to use poolling.

    Please, provide a solution, if any, as soon as possible.

    Best Regards.

    GS

  • 0 in reply to GIOVANNI STOPPONI
    TI__Mastermind 23423 points

    Hey GS,

    Unfortunately, the GPIO module will not be able to support this use case due to reasons already discussed.

    After some discussions with team, we believe an alternate solution may be possible through the EPWM Trip Edge Detection function. Does your system have 11 EPWM modules available for use? Please review the EPWM chapter of the TRM and let us know if this seems like a viable solution for your application.

    Best Regards,

    Zackary Fleenor

  • 0 in reply to Fleenor
    Prodigy 40 points

    Hi Fleenor,

    1) we have 11 free EPWM but the routing will be very complicated and we need to be really sure that we solve the problem before investing in that efford.

    I searched "Trip Edge Detection" in the TRM but I found 0 results.

    Please, explain better your solution and provide an example.

    Remember that I need to know which is the first signal that changes state.

    2) Also I have another question.

    We are considering the possibility to reduce to 9 the monitored signals and to reroute the PCB to attach each signal to a GPIO 

    that belongs only to 1 bank. This will allow us to use one ISR for each single pin (bank).

    The problem is that from the header files it seems that each core can handle only 4 GPIO ISR.

    I deduce it because we have only 4 entries in the XBAR for the GPIO interrupts:

     

    // XBAR OUTPUT MACROS

    #define GPIO_INT_XBAR_VIM_MODULE0_0        14

    #define GPIO_INT_XBAR_VIM_MODULE0_1        15

    #define GPIO_INT_XBAR_VIM_MODULE0_2        16

    #define GPIO_INT_XBAR_VIM_MODULE0_3        17

    // INTERRUPT MAP

    #define CSLR_R5FSS0_CORE0_INTR_GPIO_INTRXBAR_OUT_14                142

    #define CSLR_R5FSS0_CORE0_INTR_GPIO_INTRXBAR_OUT_15                143

    #define CSLR_R5FSS0_CORE0_INTR_GPIO_INTRXBAR_OUT_16                144

    #define CSLR_R5FSS0_CORE0_INTR_GPIO_INTRXBAR_OUT_17                145

     

    Am I right?

    Is it possible to use only 1 core to monitor these 9 signals.

    Can you suggest a solution?

    Best Regards.

    GS

  • 0 in reply to GIOVANNI STOPPONI
    TI__Expert 7586 points

    Hi 

    Will get back to you soon on this

    THanks & Regards

    Sri Vidya

  • 0 in reply to Sri Vidya Gunturi
    TI__Expert 7586 points

    Hi Giovanni

    Yes 4 GPIO Bank Interrupts are only possible per core. 

    We do have ECAP module which captures Rising edges and falling edges and rises interrupts accordingly, But this could be a over kill for GPIO Interrupts and we have only 10 ECAPs.

    The "Trip Edge Detection" that was discussed earlier is the Edge Filter Setting in the PWMs Digital Compare sub-module. PWM can be used for Edge detection. I will have to check and confirm if Edge Filter can generate any interrupts.

    Could you please explain more about the use case why 9 ISRs are required and why those GPIO Interrupts cant be handled within the bank interrupt by reading status of the pins? Is it possible to group the GPIO in 4 banks and create 4 ISRs?

    Thanks & Regards

    Sri Vidya