MSP432E401Y: Questions about ADC clock configuration (unable to get 32M adc clock under 120M system clock to obtain 2M sampling rate)

Hi Team,

When I was using the ADC module of MSP432E401Y, I found that when setting the relevant clock, only when the PLL was set to 320Mhz and the main clock was set to 80Mhz, could the ADC reach the sampling rate of 2M. In the following code, I generated the adc clock from the 320Mhz PLL through a frequency division of 5.

It seems that the reason for my issue is that the PLL has undergone a frequency division of 2 before dividing the frequency to the adc so that the clock was only half of the original clock, and the 480Mhz PLL cannot generate the 32M adc clock through a frequency division of 7.5.

Throughout the whole code, I set the SSTSH0 register of ADC0 to 0x0, trying to get 32M adc clock according to the manual.

g_ui32SysClock = SysCtlClockFreqSet((SYSCTL_XTAL_25MHZ |
            SYSCTL_OSC_MAIN |
            SYSCTL_USE_PLL |
            SYSCTL_CFG_VCO_320), 80000000); 
            
            
ADCClockConfigSet(ADC0_BASE, ADC_CLOCK_SRC_PLL | ADC_CLOCK_RATE_FULL, 5);

Kind regards,

Katherine