expert,
I am using the AM273x EVM development kit platform for radar mipi data receiving experiments(mmwave_mcuplus_sdk_04_02_00_03)。Our radar CSI2 uses 4 data lanes and 1 clock lane. The data transmission rate is 150Mbps, so the clock lane should be set to 75Mhz。We use syscfg to configure the am273 CSI2 driver。But syscfg prompts that CLK 75M cannot be set. As shown below

Set DPHY Clock in Hz This parameter is not allowed at 750MHz。DPHY Clock should be half of the mipi data rate, I require a data rate of 150Mbps, how to deal with this parameter。I tested that the DPHY Clock is set to 300MHz to receive data, but this violates the principle that the DPHY Clock should be half of the data rate.
Looking forward to your reply