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AM2634-Q1: AM2634-Q1

Part Number: AM2634-Q1
Other Parts Discussed in Thread: AM2634, TINA-TI

Hi all,

I just have a couple of questions regarding AM2634.

1-ADC

  • How much is the Input Conversion Range of ADC? What does it mean 32/18*VREFHI? Is it 32 divided by 18?
  • How much is the maximum allowable input current of ADC?
  • How many cycles does ADC need to sample the analog signal?
  • how much is the value of sample-and-hold’s capacitor?

 

2-SPI

  • what are SPI_D0 and SPI_D1? How we could map them into MISO and MOSI?

3-LIN

  • Is there any internal pull-up resistor in LINRXD pin of MCU or do we need to use external pull-up resistor?


thank you

  • Hi,

    I have assigned this ticket to our subject matter expert.

    Thanks 

  • Hello Madhi,


    1) ADC

    1a) The input conversion range is between 0 V and 3.2 V (Assuming internal 1.8 VREFHI source or high-precision external 1.8 VREFHI source)

    1b) Maximum allowable input current is << 8 mA

    1c) The minimum allowable sample time is 75 ms and the ADC clock operates at 50 MHz (20 ns period). The conversion time after Sample+Hold is 250 ns. 

    1d) The Hold capacitor (CH) is 8 pF in this design. Please refer to the AM263x TINA model and associated app note shared below.

     ADC Input Circuit Evaluation for C2000 MCUs (TINA-TI) Application Report: https://www.ti.com/lit/pdf/SPRACT6

     AM263x 12B ADC Model: /cfs-file/__key/communityserver-discussions-components-files/908/AM263x_5F00_12BSE.zip

        


    2) SPI

    2a) These details and much more information can be found in the Peripherals - General Connectivity Peripherals - MCSPI chapter of the TRM. (AM263x Technical Reference Manual)

        


    3) LIN

    3a) Yes, LINRXD and LINTXD are implemented/muxed on pins that utilize the typical LVCMOS voltage buffer. The associated PADCONFIG registers can be configured with internal pull up/down resistors enabled. However, note that this is a weak pull resistor and including a parallel external pull resistor will increase the system/interface reliability.

        


    Best Regards,

    Zackary Fleenor