Looking for some clarity on the nError pins on the TMS570LC4357. On page 324 of the TRM https://www.ti.com/lit/ug/spnu563a/spnu563a.pdf?ts=1658430759684&ref_url=https%253A%252F%252Fwww.google.com.mx%252F, I see that if the CPUs are run in lockstep, only ESM1 is active. I am curious, if the CPUs are running in lockstep and only ESM1 is active, is nError2 still accessible as an input pin? Also, are nError1 and nError2 both mapped to GIOB[6]/J2?
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