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TMS570LC4357: ESM 1.2 is not set when testing DMA memory protection (DMA9A)

Max Wittekind
Expert 1875 points
Part Number: TMS570LC4357

Hi experts,

During the implementation of the DMA9A Diagnostic mentioned in the Safety Manual, we noticed that ESM 1.2 does not get set on the forced memory access violation of the dma.
However the REG0FT bit gets set (we are testing region0).
Based on this, the test seems to work as intended, but signalling the error to esm seems to be disabled.

But we noticed that ESM 1.2 Error is set, when INT0ENA is set. As far as we understand, this bit enables all interrupts of the dma module region 0.

(Q1) Is the signalling of the ESM error dependend on the enable state of all dma-interrupts?

(Q2) If this is the case, how can we enable ESM error signalling without using the dma Interrupts FTC, LFS, HBC, and BTC ?

Thank you and best regards,
Max

  • 0
    TI__Guru 70551 points

    Hi Max,

    I started to look into your issue and i will provide an update very soon.

    --

    Thanks & Regards,
    Jagadish.

  • 0 in reply to jagadish gundavarapu
    TI__Guru 70551 points

    Hi Max,

    Is it possible for you to share your code for quick debugging?

    --

    Thanks & Regards,

    Jagadish.

  • 0 in reply to jagadish gundavarapu
    Expert 1875 points

    Hi Jagadish,

    Unfortenatly I can not share my code. But here the steps of the test. the goal is to set a read-only region and then try to write to it. We expect to see that the error bits and ESM 1.2 is set.

    1. Set a ProtectedRogion: by setting the Adress in DMA MPR0S Register and DMA MPR0E with the adress + sizeof(uint32)
    2. Set REG0ENA bit to 1
    3. Set INT0ENA bit to 0

    4. Set REG0AP to read only
    5. Set INT0ENA to 1 (Is setting INT0ENA necessary for EMS 1.2 to be signalled?)
    6. Set the DMA CTRL packet
      6.1 ISADDR = source address
      6.2 IDADDR = destination address
      6.3 IFTCOUNT to 1
      6.4 IECOUNT to 1
      6.5 RES to 2 
      6.6 WES to 2
      6.7 TTYPE to 0
      6.8 ADDMR to 0
      6.9 ADDMW to 0
      6.10 AIM to 0
      6.11 CHAIN to 0
      6.12 EIDXD to 0
      6.13 EIDXS to 0
      6.14 FIDXD to 0
      6.15 FIDXS to 0
      6.16 CH0PA - PORTA to 2

    7. Set SWCHENA to 1
    8. Set DMA_EN bit to 1
    9. wait for DMA_BUSBUSY == 0

    10. Check data data at source adress != data at destination address
    11. Check Error Bits and ESM 1.2
    12 Disable dma

  • +1 in reply to Max Wittekind
    TI__Guru 70551 points

    Hi Max,

    Max Wittekind said:
    (Q1) Is the signalling of the ESM error dependend on the enable state of all dma-interrupts?

    Not on all the DMA interrupts, the ESM 1.2 error will be dependent on the state of the MPU related interrupts only.

    Max Wittekind said:
    (Q2) If this is the case, how can we enable ESM error signalling without using the dma Interrupts FTC, LFS, HBC, and BTC ?

    This is not the case, there is not relation between ESM1.2 and FTC, LFS, HBC and BTC interrupts.

    It will just depends on MPU region wise interrupts like INT0ENA, INT1ENA, INT2ENA and INT3ENA.

    refer 20.3.1.64 DMA Memory Protection Control Register 1 for more details.

    --

    Thanks & regards,
    Jagadish.