Other Parts Discussed in Thread: TM4C1294KCPDT
Hello,
I had the watchdog timer 0 enabled from migrated Stellaris code but TM4C1294 watchdog timer 0 has issues. For one writing WDTLOAD values lower than the current down count are just ignored. Tivaware uses = to write the value to WDTLOAD register value so values > the current WDLOAD are just ignored in the unlocked condition. Change Tiva function WDTLOAD write |= allows a greater timeout value to update watchdog 0 in the down counts. However, writes of lower WDTLOAD values will still be ignored. That is the errata condition as no shadow update ability and clearing WDTLOAD 0x0 triggers immediate interrupt.
Unless you use CCS debug to check the WDTLOAD register has changed after the unlocked register write event you would never know it did not and your hardware would Not be protected 
Example: Changing WDTLOAD value from microseconds timeout to several seconds it can never be changed back to a lower value unless you run code snip below. This post informs TM4C1294 watchdog timer 0 has other undocumented errata. The code below can handle 2 defined WDTLOAD times to switch between or reduce the timeout once WDTLOAD has been set to greater value by Tivaware update writes WDTLOAD register via |= syntax.
/* Unlock the Watchdodgs registers for write access */
HWREG(WATCHDOG0_BASE + WDT_O_LOCK) = WDT_LOCK_UNLOCK;
/* Time writes to WDTLOAD occurs below current down count value */
while(HWREG(WATCHDOG0_BASE + WDT_O_VALUE) >= WATCHDOG0_HI_RELOAD_VALUE)
{
/* Reset Watchdog-0 for lower WDTLOAD write values */
HWREG(WATCHDOG0_BASE + WDT_O_LOAD) = WATCHDOG0_MED_RELOAD_VALUE;
/* Check ok to lock the WDog0 registers */
if(HWREG(WATCHDOG0_BASE + WDT_O_LOAD) <= WATCHDOG0_MED_RELOAD_VALUE)
{
/* Lock the Watchdodg registers blocking write access. */
HWREG(WATCHDOG0_BASE + WDT_O_LOCK) = WDT_LOCK_LOCKED;
break;
}
}
